[U-Boot] [PATCH 01/22][v2] armv8/ls2085ardb: Add eth & phy f/w loading support

[U-Boot] [PATCH 01/22][v2] armv8/ls2085ardb: Add eth & phy f/w loading support

[Prabhakar Kushwaha]

Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.

Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Sending as it is for patch set

 board/freescale/ls2085ardb/Makefile        |   2 +-
 board/freescale/ls2085ardb/eth_ls2085rdb.c | 133 +++++++++++++++++++++++++++++
 board/freescale/ls2085ardb/ls2085ardb.c    |  13 ---
 include/configs/ls2085ardb.h               |  23 +++++
 4 files changed, 157 insertions(+), 14 deletions(-)
 create mode 100644 board/freescale/ls2085ardb/eth_ls2085rdb.c

diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile
index 0bfe21c..de383cc 100644
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2085ardb/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085ardb.o
+obj-y += ls2085ardb.o eth_ls2085rdb.o
 obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c
new file mode 100644
index 0000000..60af079
--- /dev/null
+++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+int load_firmware_cortina(struct phy_device *phy_dev)
+{
+	if (phy_dev->drv->config)
+		return phy_dev->drv->config(phy_dev);
+
+	return 0;
+}
+
+void load_phy_firmware(void)
+{
+	int i;
+	u8 phy_addr;
+	struct phy_device *phy_dev;
+	struct mii_dev *dev;
+	phy_interface_t interface;
+
+	/*Initialize and upload firmware for all the PHYs*/
+	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
+		interface = wriop_get_enet_if(i);
+		if (interface == PHY_INTERFACE_MODE_XGMII) {
+			dev = wriop_get_mdio(i);
+			phy_addr = wriop_get_phy_address(i);
+			phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
+						interface);
+			if (!phy_dev) {
+				printf("No phydev for phyaddr %d\n", phy_addr);
+				continue;
+			}
+
+			/*Flash firmware for All CS4340 PHYS */
+			if (phy_dev->phy_id == PHY_UID_CS4340)
+				load_firmware_cortina(phy_dev);
+		}
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+	int i, interface;
+	struct memac_mdio_info mdio_info;
+	struct mii_dev *dev;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+	struct memac_mdio_controller *reg;
+
+	srds_s1 = in_le32(&gur->rcwsr[28]) &
+				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+	/* Register the EMI 1 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+	mdio_info.regs = reg;
+	mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+	/* Register the EMI 2 */
+	fm_memac_mdio_init(bis, &mdio_info);
+
+	switch (srds_s1) {
+	case 0x2A:
+		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+		wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
+
+		break;
+	default:
+		printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
+		interface = wriop_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
+		switch (wriop_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+			wriop_set_mdio(i, dev);
+			break;
+		default:
+			break;
+		}
+	}
+
+	/* Load CORTINA CS4340 PHY firmware */
+	load_phy_firmware();
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index d05f2bc..6cb7b13 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -176,19 +176,6 @@ unsigned long get_dram_size_to_hide(void)
 	return dram_to_hide;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	int error = 0;
-
-#ifdef CONFIG_FSL_MC_ENET
-	error = cpu_eth_init(bis);
-#endif
-
-	error = pci_eth_init(bis);
-
-	return error;
-}
-
 #ifdef CONFIG_FSL_MC_ENET
 void fdt_fixup_board_enet(void *fdt)
 {
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index d1c2548..62f13f9 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -302,4 +302,27 @@ unsigned long get_board_sys_clk(void);
 	"kernel_load=0xa0000000\0"		\
 	"kernel_size=0x1000000\0"
 
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHYLIB
+#define	CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR		0x581000000
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+
+#define CORTINA_PHY_ADDR1	0x10
+#define CORTINA_PHY_ADDR2	0x11
+#define CORTINA_PHY_ADDR3	0x12
+#define CORTINA_PHY_ADDR4	0x13
+#define AQ_PHY_ADDR1		0x00
+#define AQ_PHY_ADDR2		0x01
+#define AQ_PHY_ADDR3		0x02
+#define AQ_PHY_ADDR4		0x03
+
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_PHY_GIGE
+#endif
+
 #endif /* __LS2_RDB_H */
-- 
1.9.1

[U-Boot] [PATCH 02/22][v2] armv8/ls2085ardb: add hwconfig setting for eSDHC

[Prabhakar Kushwaha]

From: Yangbo Lu <yangbo.lu@freescale.com>

Add hwconfig setting for eSDHC since it shares some pins with other
IP block.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Sending as it is for patch set

 board/freescale/ls2085ardb/ls2085ardb.c | 36 +++++++++++++++++++++++++++++++++
 include/configs/ls2085ardb.h            |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 6cb7b13..e0a8a41 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -10,6 +10,7 @@
 #include <fsl_ifc.h>
 #include <fsl_ddr.h>
 #include <asm/io.h>
+#include <hwconfig.h>
 #include <fdt_support.h>
 #include <libfdt.h>
 #include <fsl_debug_server.h>
@@ -21,8 +22,15 @@
 #include "../common/qixis.h"
 #include "ls2085ardb_qixis.h"
 
+#define PIN_MUX_SEL_SDHC	0x00
+
+#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	MUX_TYPE_SDHC,
+};
+
 unsigned long long get_qixis_addr(void)
 {
 	unsigned long long addr;
@@ -129,6 +137,34 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int config_board_mux(int ctrl_type)
+{
+	u8 reg5;
+
+	reg5 = QIXIS_READ(brdcfg[5]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_SDHC:
+		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
+		break;
+	default:
+		printf("Wrong mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[5], reg5);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	if (hwconfig("sdhc"))
+		config_board_mux(MUX_TYPE_SDHC);
+
+	return 0;
+}
+
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 62f13f9..29c934e 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -288,6 +288,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_DOS_PARTITION
 #endif
 
+#define CONFIG_MISC_INIT_R
+
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS		\
-- 
1.9.1

[U-Boot] [PATCH 03/22][v2] armv8/ls2085a: Enable Date command for QDS and RDB

[Prabhakar Kushwaha]

From: Priyanka Jain <Priyanka.Jain@freescale.com>

Enable Date command for QDS and RDB boards

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Sending as it is for patch set

 include/configs/ls2085aqds.h | 1 +
 include/configs/ls2085ardb.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 711d529..87e9333 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -288,6 +288,7 @@ unsigned long get_board_ddr_clk(void);
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 29c934e..ad618a8 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -253,6 +253,7 @@ unsigned long get_board_sys_clk(void);
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-- 
1.9.1

[U-Boot] [PATCH 04/22][v2] armv8/ls2085aqds: Add support of SerDes protocol 0x49

[Prabhakar Kushwaha]

SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.

Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Incorporated York's commets
 - updated subject and description

 board/freescale/ls2085aqds/eth.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index 5ba4770..f32ace2 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -210,6 +210,7 @@ static void initialize_dpmac_to_slot(void)
 	switch (serdes2_prtcl) {
 	case 0x07:
 	case 0x08:
+	case 0x49:
 		printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n",
 		       serdes2_prtcl);
 		lane_to_slot_fsm2[0] = EMI1_SLOT4;
@@ -247,6 +248,7 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
 	switch (serdes2_prtcl) {
 	case 0x07:
 	case 0x08:
+	case 0x49:
 		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 							(dpmac_id - 9));
 		slot = lane_to_slot_fsm2[lane];
-- 
1.9.1

[U-Boot] [PATCH 05/22][v2] armv8/ls2085a: Update LS2085a PCIe compatible

[Prabhakar Kushwaha]

Compatible field "fsl,20851a-pcie" is not correct.
So update it to "fsl,ls2085a-pcie"

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: New patch

 include/configs/ls2085a_common.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index e270fc8..749c58d 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -186,7 +186,8 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_PCIE2		/* PCIE controler 2 */
 #define CONFIG_PCIE3		/* PCIE controler 3 */
 #define CONFIG_PCIE4		/* PCIE controler 4 */
-#define FSL_PCIE_COMPAT "fsl,20851a-pcie"
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
 
 #define CONFIG_SYS_PCI_64BIT
 
-- 
1.9.1

[U-Boot] [PATCH 06/22][v2] armv8/ls2085a: call ft_pcie_setup() to change dts status

[Prabhakar Kushwaha]

call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCW

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: Incorporated York's comments

 arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index d370023..b9fd559 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -69,6 +69,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
 #if defined(CONFIG_FSL_ESDHC)
 	fdt_fixup_esdhc(blob, bd);
 #endif
-- 
1.9.1

[U-Boot] [PATCH 07/22][v2] armv8/ls2085qds: Update SFP TX bit as "0" to enable XFI

[Prabhakar Kushwaha]

FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.

Signed-off-by: Dai Haruki <Dai.Haruki@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085aqds/eth.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c
index f32ace2..1f8a31f 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2085aqds/eth.c
@@ -53,7 +53,7 @@ static int riser_phy_addr[] = {
 #define EMI1_SLOT5	4
 #define EMI1_SLOT6	5
 #define EMI2		6
-#define SFP_TX		1
+#define SFP_TX		0
 
 static const char * const mdio_names[] = {
 	"LS2085A_QDS_MDIO0",
-- 
1.9.1

[U-Boot] [PATCH 08/22][v2] armv8/ls2085rdb: Update PCA9547PW slave address

[Prabhakar Kushwaha]

Primary Mux on I2C1 controller has slave address as 0x75.
So update its address.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Changes for v2: Incorporated York's comments

 include/configs/ls2085ardb.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index ad618a8..dab03bc 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -241,8 +241,8 @@ unsigned long get_board_sys_clk(void);
 /*
  * I2C
  */
-#define I2C_MUX_PCA_ADDR		0x77
-#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+#define I2C_MUX_PCA_ADDR		0x75
+#define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
-- 
1.9.1

[U-Boot] [PATCH 09/22][v2] armv8/ls2085a: Increase the supported kernel size

[Prabhakar Kushwaha]

From: Bhupesh Sharma <bhupesh.sharma@freescale.com>

Increases the kernel size supported for LS2085A platforms:-
 - Update environment variables
 - Add ramdisk_size in bootargs env variable
 - Define  CONFIG_SYS_BOOTM_LEN to 64MB

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 include/configs/ls2085a_common.h | 9 ++++++---
 include/configs/ls2085aqds.h     | 2 +-
 include/configs/ls2085ardb.h     | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 749c58d..a33b8a9 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -248,13 +248,13 @@ unsigned long long get_qixis_addr(void);
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581200000\0"		\
 	"kernel_load=0xa0000000\0"		\
-	"kernel_size=0x1000000\0"		\
+	"kernel_size=0x2000000\0"		\
 	"console=ttyAMA0,38400n8\0"
 
 #define CONFIG_BOOTARGS		"console=ttyS1,115200 root=/dev/ram0 " \
 				"earlycon=uart8250,mmio,0x21c0600,115200 " \
-				"default_hugepagesz=2m hugepagesz=2m " \
-				"hugepages=16"
+				"ramdisk_size=0x2000000 default_hugepagesz=2m" \
+				" hugepagesz=2m hugepages=16"
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
 #define CONFIG_BOOTDELAY		10
@@ -301,4 +301,7 @@ unsigned long get_dram_size_to_hide(void);
 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 87e9333..8cb8c78 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -336,7 +336,7 @@ unsigned long get_board_ddr_clk(void);
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
-	"kernel_size=0x1000000\0"
+	"kernel_size=0x2000000\0"
 
 #ifdef CONFIG_FSL_MC_ENET
 #define CONFIG_FSL_MEMAC
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index dab03bc..ba671dd 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -303,7 +303,7 @@ unsigned long get_board_sys_clk(void);
 	"initrd_high=0xffffffffffffffff\0"	\
 	"kernel_start=0x581100000\0"		\
 	"kernel_load=0xa0000000\0"		\
-	"kernel_size=0x1000000\0"
+	"kernel_size=0x2000000\0"
 
 /* MAC/PHY configuration */
 #ifdef CONFIG_FSL_MC_ENET
-- 
1.9.1

[U-Boot] [PATCH 10/22][v2] board/fsl/common: Fix eeprom system version endianness

[Prabhakar Kushwaha]

From: Jaiprakash Singh <b44839@freescale.com>

SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.

So use cpu-specific APIs to read SYSTEM version.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/common/sys_eeprom.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 5cb7570..29aa778 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
 	/* EEPROM tag ID, either CCID or NXID */
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-	       e.version);
+	       be32_to_cpu(e.version));
 #else
 	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
@@ -340,7 +340,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (cmd == 'i') {
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 		memcpy(e.id, "NXID", sizeof(e.id));
-		e.version = NXID_VERSION;
+		e.version = cpu_to_be32(NXID_VERSION);
 #else
 		memcpy(e.id, "CCID", sizeof(e.id));
 #endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-	       e.version);
+	       be32_to_cpu(e.version));
 #else
 	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
@@ -496,7 +496,7 @@ int mac_read_from_eeprom(void)
 	 * that at boot time, U-Boot will still say "NXID v0".
 	 */
 	if (e.version == 0) {
-		e.version = NXID_VERSION;
+		e.version = cpu_to_be32(NXID_VERSION);
 		update_crc();
 	}
 #endif
-- 
1.9.1

[U-Boot] [PATCH 11/22][v2] armv8/ls2085RDB: Update board version print logic

[Prabhakar Kushwaha]

As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.

So update board version print logic to reflect the same.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085ardb/ls2085ardb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index e0a8a41..ff4b6a0 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -56,7 +56,7 @@ int checkboard(void)
 	sw = QIXIS_READ(arch);
 	printf("Board: %s, ", CONFIG_IDENT_STRING);
 	printf("Board Arch: V%d, ", sw >> 4);
-	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-- 
1.9.1

[U-Boot] [PATCH 12/22][v2] armv8/fsl-lsch3: Fix DDR speed message

[Prabhakar Kushwaha]

From: York Sun <yorksun@freescale.com>

DDR speed should be in MT/s, not MHz.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 6714577..19c3995 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -394,8 +394,8 @@ int print_cpuinfo(void)
 	}
 	printf("\n       Bus:      %-4s MHz  ",
 	       strmhz(buf, sysinfo.freq_systembus));
-	printf("DDR:      %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
-	printf("     DP-DDR:   %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
+	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+	printf("     DP-DDR:   %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
 	puts("\n");
 
 	/* Display the RCW, so that no one gets confused as to what RCW
-- 
1.9.1

[U-Boot] [PATCH 13/22][v2] armv8/fsl-ch3: Add support to print SoC personality

[Prabhakar Kushwaha]

This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 arch/arm/cpu/armv8/fsl-lsch3/cpu.c        | 37 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch3/soc.h | 20 +++++++++++++++++
 2 files changed, 57 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 19c3995..52bc731 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -9,6 +9,7 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
+#include <asm/arch-fsl-lsch3/soc.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
@@ -22,6 +23,35 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct cpu_type cpu_type_list[] = {
+#ifdef CONFIG_LS2085A
+	CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+	CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+	CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+#endif
+};
+
+void cpu_name(char *name)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	unsigned int i, svr, ver;
+
+	svr = in_le32(&gur->svr);
+	ver = SVR_SOC_VER(svr);
+
+	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+		if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
+			strcpy(name, cpu_type_list[i].name);
+
+			if (IS_E_PROCESSOR(svr))
+				strcat(name, "E");
+			break;
+		}
+
+	if (i == ARRAY_SIZE(cpu_type_list))
+		strcpy(name, "unknown");
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
@@ -380,6 +410,13 @@ int print_cpuinfo(void)
 	unsigned int i, core;
 	u32 type;
 
+	puts("SoC: ");
+
+	cpu_name(buf);
+	printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
+
+	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
 	get_sys_info(&sysinfo);
 	puts("Clock Configuration:");
 	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
index 16b723d..9a29272 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -4,5 +4,25 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+struct cpu_type {
+	char name[15];
+	u32 soc_ver;
+	u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E		0xFFFFFE
+#define SVR_LS2045		0x870120
+#define SVR_LS2080		0x870110
+#define SVR_LS2085		0x870100
+
+#define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
+#define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
+
 void fsl_lsch3_early_init_f(void);
+void cpu_name(char *name);
 
-- 
1.9.1

[U-Boot] [PATCH 14/22][v2] armv8/ls2085a: Avoid hard-coding for board name print

[Prabhakar Kushwaha]

LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.

Instead of hard-coding, board name should change as per selected
personality.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085aqds/ls2085aqds.c | 6 +++++-
 board/freescale/ls2085ardb/ls2085ardb.c | 5 ++++-
 include/configs/ls2085aqds.h            | 3 ---
 include/configs/ls2085ardb.h            | 3 ---
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 6a22122..27a23ec 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -49,11 +49,15 @@ int checkboard(void)
 					    "100 separate SSCG"};
 	int clock;
 
+	cpu_name(buf);
+	printf("Board: %s-QDS, ", buf);
+
 	sw = QIXIS_READ(arch);
-	printf("Board: %s, ", CONFIG_IDENT_STRING);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 
+	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
+
 	sw = QIXIS_READ(brdcfg[0]);
 	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index ff4b6a0..5f25328 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -52,9 +52,12 @@ unsigned long long get_qixis_addr(void)
 int checkboard(void)
 {
 	u8 sw;
+	char buf[15];
+
+	cpu_name(buf);
+	printf("Board: %s-RDB, ", buf);
 
 	sw = QIXIS_READ(arch);
-	printf("Board: %s, ", CONFIG_IDENT_STRING);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index 8cb8c78..731eca2 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -10,9 +10,6 @@
 #include "ls2085a_common.h"
 #include <config_cmd_default.h>
 
-#define CONFIG_IDENT_STRING		" LS2085A-QDS"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-QDS"
-
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifndef __ASSEMBLY__
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index ba671dd..5a5884c 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -10,9 +10,6 @@
 #include "ls2085a_common.h"
 #include <config_cmd_default.h>
 
-#define CONFIG_IDENT_STRING		" LS2085A-RDB"
-#define CONFIG_BOOTP_VCI_STRING		"U-boot.LS2085A-RDB"
-
 #undef CONFIG_CONS_INDEX
 #define CONFIG_CONS_INDEX       2
 
-- 
1.9.1

[U-Boot] [PATCH 15/22][v2] driver/ddr/fsl: Add a hook to update SPD address

[Prabhakar Kushwaha]

From: York Sun <yorksun@freescale.com>

In case SPD address changes between board revisions, updating SPD
address can be called from board file.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 drivers/ddr/fsl/main.c | 8 ++++++++
 include/fsl_ddr.h      | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index fa22383..14ecf12 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -135,6 +135,13 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
 __attribute__((weak, alias("__get_spd")))
 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 
+/* This function allows boards to update SPD address */
+__weak void update_spd_address(unsigned int ctrl_num,
+			       unsigned int slot,
+			       unsigned int *addr)
+{
+}
+
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 		      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 {
@@ -148,6 +155,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 
 	for (i = 0; i < dimm_slots_per_ctrl; i++) {
 		i2c_address = spd_i2c_addr[ctrl_num][i];
+		update_spd_address(ctrl_num, i, &i2c_address);
 		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 	}
 }
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 4099a74..728503b 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -136,4 +136,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 			unsigned int controller_number,
 			unsigned int dimm_number);
+void update_spd_address(unsigned int ctrl_num,
+			unsigned int slot,
+			unsigned int *addr);
 #endif
-- 
1.9.1

[U-Boot] [PATCH 16/22][v2] armv8/ls2085ardb: Fix SPD address error on early boards

[Prabhakar Kushwaha]

From: York Sun <yorksun@freescale.com>

Board rev C and earlier has duplicated SPD address on 2nd DDR
controller slots. It is fixed on rev D and later. SPD addresses
need to be updated accordingly.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085ardb/ls2085ardb.c | 19 +++++++++++++++++++
 include/configs/ls2085ardb.h            |  4 ++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 5f25328..abe2114 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -273,3 +273,22 @@ void qixis_dump_switch(void)
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
 }
+
+/*
+ * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
+ * Both slots has 0x54, resulting 2nd slot unusable.
+ */
+void update_spd_address(unsigned int ctrl_num,
+			unsigned int slot,
+			unsigned int *addr)
+{
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	if ((sw & 0xf) < 0x3) {
+		if (ctrl_num == 1 && slot == 0)
+			*addr = SPD_EEPROM_ADDRESS4;
+		else if (ctrl_num == 1 && slot == 1)
+			*addr = SPD_EEPROM_ADDRESS3;
+	}
+}
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index 5a5884c..a0f0f6c 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -29,8 +29,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS1	0x51
 #define SPD_EEPROM_ADDRESS2	0x52
-#define SPD_EEPROM_ADDRESS3	0x54
-#define SPD_EEPROM_ADDRESS4	0x53	/* Board error */
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
 #define SPD_EEPROM_ADDRESS5	0x55
 #define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
-- 
1.9.1

[U-Boot] [PATCH 17/22][v2] armv8/ls2085a: Expose all DDR region(s) to Linux

[Prabhakar Kushwaha]

From: Bhupesh Sharma <bhupesh.sharma@freescale.com>

This patch allows u-boot to expose the complete DDR region(s) to Linux
(after subtracting the memory hidden via MEM_TOP_HIDE mechanism).

This allows the u-boot to support the 48-bit VA support provided by
ARM64 Linux in flavors 3.18 and above, by passing the appropriate
'memory' DTS nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085a/README          | 11 +++++++++++
 board/freescale/ls2085a/ls2085a.c       | 15 +++++++++------
 board/freescale/ls2085aqds/README       | 19 +++++++++++++++++++
 board/freescale/ls2085aqds/ls2085aqds.c | 15 +++++++++------
 board/freescale/ls2085ardb/README       | 11 +++++++++++
 board/freescale/ls2085ardb/ls2085ardb.c | 15 +++++++++------
 6 files changed, 68 insertions(+), 18 deletions(-)

diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README
index b7023e1..bc1d0bb 100644
--- a/board/freescale/ls2085a/README
+++ b/board/freescale/ls2085a/README
@@ -14,3 +14,14 @@ Memory map from core's view
 
 Other addresses are either reserved, or not used directly by u-boot.
 This list should be updated when more addresses are used.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+   hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index dd0acf2..e43dd4c 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -127,15 +127,18 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	phys_addr_t base;
-	phys_size_t size;
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	ft_cpu_setup(blob, bd);
 
-	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README
index fb3938e..11b2e79 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2085aqds/README
@@ -127,3 +127,22 @@ b) NOR boot
 c) NAND boot
 d) SD boot
 e) QSPI boot
+
+Environment Variables
+---------------------
+- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
+  the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+- mcmemsize: MC DRAM block size. If this variable is not defined
+  the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+   hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 27a23ec..9b57799 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -244,15 +244,18 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	phys_addr_t base;
-	phys_size_t size;
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	ft_cpu_setup(blob, bd);
 
-	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README
index cfd5185..2f18243 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2085ardb/README
@@ -107,3 +107,14 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+
+Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
+-------------------------------------------------------------------
+One needs to use appropriate bootargs to boot Linux flavors which do
+not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
+below:
+
+=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram
+   earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
+   hugepages=16 mem=2048M'
+
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index abe2114..15cb251 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -241,15 +241,18 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-	phys_addr_t base;
-	phys_size_t size;
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
 
 	ft_cpu_setup(blob, bd);
 
-	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
+	/* fixup DT for the two GPP DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-- 
1.9.1

[U-Boot] [PATCH 18/22][v2] armv8/ls2085a: Update SoC README for DDR layout

[Prabhakar Kushwaha]

Update SoC README to provide details of
 - Memory regions
 - Memory used by MC and Debug server

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Chanes for v2: New patch

 arch/arm/cpu/armv8/fsl-lsch3/README | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index 37f07fb..3c15479 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -9,6 +9,31 @@ Freescale LayerScape with Chassis Generation 3
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
 for example LS2085A.
 
+DDR Layout
+============
+Entire DDR region splits into two regions.
+ - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
+ - Region 2 is at 0x80_8000_0000 to the top of total memory,
+   for example 16GB, 0x83_ffff_ffff.
+
+All DDR memory is marked as cache-enabled.
+
+When MC and Debug server is enabled, they carve 512MB away from the high
+end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
+with MC and Debug server enabled. Linux only sees 15.5GB.
+
+The reserved 512MB layout looks like
+
+   +---------------+ <-- top/end of memory
+   |    256MB      |  debug server
+   +---------------+
+   |    256MB      |  MC
+   +---------------+
+   |     ...       |
+
+MC requires the memory to be aligned with 512MB, so even debug server is
+not enabled, 512MB is reserved, not 256MB.
+
 Flash Layout
 ============
 
-- 
1.9.1

[U-Boot] [PATCH 19/22][v2] driver/fsl_debug_server: Fix the DDR hide logic for LS2085a

[Prabhakar Kushwaha]

From: Bhupesh Sharma <bhupesh.sharma@freescale.com>

This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 drivers/misc/fsl_debug_server.c | 5 +++++
 drivers/net/fsl-mc/mc.c         | 8 --------
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/misc/fsl_debug_server.c b/drivers/misc/fsl_debug_server.c
index e080fe6..44cd9b9 100644
--- a/drivers/misc/fsl_debug_server.c
+++ b/drivers/misc/fsl_debug_server.c
@@ -10,6 +10,7 @@
 #include <asm/system.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
 
+#include <fsl-mc/fsl_mc.h>
 #include <fsl_debug_server.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -151,6 +152,10 @@ int debug_server_init(void)
 		debug_server_ram_addr =
 			gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
 
+#ifdef CONFIG_FSL_MC_ENET
+	debug_server_ram_addr += mc_get_dram_block_size();
+#endif
+
 	error = debug_server_parse_firmware_fit_image(&raw_image_addr,
 							&raw_image_size);
 	if (error != 0)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index c5c44bc..f4a050a 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -9,7 +9,6 @@
 #include <fsl-mc/fsl_mc_sys.h>
 #include <fsl-mc/fsl_mc_private.h>
 #include <fsl-mc/fsl_dpmng.h>
-#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_dprc.h>
 #include <fsl-mc/fsl_dpio.h>
 #include <fsl-mc/fsl_qbman_portal.h>
@@ -403,13 +402,6 @@ int mc_init(void)
 			gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
 	}
 
-#ifdef CONFIG_FSL_DEBUG_SERVER
-	/*
-	 * FIXME: I don't think this is right. See get_dram_size_to_hide()
-	 */
-		mc_ram_addr -= debug_server_get_dram_block_size();
-#endif
-
 	error = calculate_mc_private_ram_params(mc_ram_addr,
 						mc_ram_size,
 						&mc_ram_aligned_base_addr,
-- 
1.9.1

[U-Boot] [PATCH 20/22][v2] arm/errata: Update required bits for A57 cores erratas

[Prabhakar Kushwaha]

From: Bhupesh Sharma <bhupesh.sharma@freescale.com>

This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 arch/arm/cpu/armv8/start.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e5f2766..e70bed4 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -115,18 +115,18 @@ apply_a57_core_errata:
 #ifdef CONFIG_ARM_ERRATA_828024
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
 	/* Disable non-allocate hint of w-b-n-a memory type */
-	mov	x0, #0x1 << 49
+	orr	x0, x0, #1 << 49
 	/* Disable write streaming no L1-allocate threshold */
-	mov	x0, #0x3 << 25
+	orr	x0, x0, #3 << 25
 	/* Disable write streaming no-allocate threshold */
-	mov	x0, #0x3 << 27
+	orr	x0, x0, #3 << 27
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_826974
 	mrs	x0, S3_1_c15_c2_0	/* cpuactlr_el1 */
 	/* Disable speculative load execution ahead of a DMB */
-	mov	x0, #0x1 << 59
+	orr	x0, x0, #1 << 59
 	msr	S3_1_c15_c2_0, x0	/* cpuactlr_el1 */
 #endif
 
-- 
1.9.1

[U-Boot] [PATCH 21/22][v2] armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr

[Prabhakar Kushwaha]

From: Stuart Yoder <stuart.yoder@freescale.com>

The agreed split of the top of memory is 256M for debug server and 256M
for MC. This patch implements the split.

In addition, the MC mem must be 512MB aligned, so the amount of memory
to hide must be 512MB to achieve that alignment.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 board/freescale/ls2085a/ls2085a.c       |  2 +-
 board/freescale/ls2085aqds/ls2085aqds.c |  2 +-
 board/freescale/ls2085ardb/ls2085ardb.c |  2 +-
 include/configs/ls2085a_common.h        | 12 +++++++++---
 4 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index e43dd4c..73c4410 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -80,7 +80,7 @@ unsigned long get_dram_size_to_hide(void)
 	dram_to_hide += mc_get_dram_block_size();
 #endif
 
-	return dram_to_hide;
+	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
index 9b57799..c492c7e 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2085aqds/ls2085aqds.c
@@ -215,7 +215,7 @@ unsigned long get_dram_size_to_hide(void)
 	dram_to_hide += mc_get_dram_block_size();
 #endif
 
-	return dram_to_hide;
+	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
 }
 
 #ifdef CONFIG_FSL_MC_ENET
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c
index 15cb251..1f8cf8a 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2085ardb/ls2085ardb.c
@@ -212,7 +212,7 @@ unsigned long get_dram_size_to_hide(void)
 	dram_to_hide += mc_get_dram_block_size();
 #endif
 
-	return dram_to_hide;
+	return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
 }
 
 #ifdef CONFIG_FSL_MC_ENET
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index a33b8a9..214d790 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -163,21 +163,27 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
 
 /* Debug Server firmware */
-#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
 /* 2 sec timeout */
 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
 
 /* MC firmware */
 #define CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 
-/* Carve out a DDR region which will not be used by u-boot/Linux */
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
+#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(256UL * 1024 * 1024)
+#define CONFIG_SYS_MEM_TOP_HIDE_MIN			(512UL * 1024 * 1024)
 #define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()
 #endif
 
-- 
1.9.1

[U-Boot] [PATCH 22/22][v2] armv8/ls2085a: enable debug server

[Prabhakar Kushwaha]

From: Stuart Yoder <stuart.yoder@freescale.com>

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Changes for v2: sending as it is for patch set

 include/configs/ls2085a_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 214d790..cf51909 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -163,6 +163,7 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
 
 /* Debug Server firmware */
+#define CONFIG_FSL_DEBUG_SERVER
 /* 2 sec timeout */
 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
 
-- 
1.9.1

[U-Boot] [PATCH 09/22][v2] armv8/ls2085a: Increase the supported kernel size

[York Sun]

On 05/28/2015 02:24 AM, Prabhakar Kushwaha wrote:
> From: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> 
> Increases the kernel size supported for LS2085A platforms:-
>  - Update environment variables
>  - Add ramdisk_size in bootargs env variable
>  - Define  CONFIG_SYS_BOOTM_LEN to 64MB
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Changes for v2: sending as it is for patch set
> 
>  include/configs/ls2085a_common.h | 9 ++++++---
>  include/configs/ls2085aqds.h     | 2 +-
>  include/configs/ls2085ardb.h     | 2 +-
>  3 files changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
> index 749c58d..a33b8a9 100644
> --- a/include/configs/ls2085a_common.h
> +++ b/include/configs/ls2085a_common.h
> @@ -248,13 +248,13 @@ unsigned long long get_qixis_addr(void);
>  	"initrd_high=0xffffffffffffffff\0"	\
>  	"kernel_start=0x581200000\0"		\
>  	"kernel_load=0xa0000000\0"		\
> -	"kernel_size=0x1000000\0"		\
> +	"kernel_size=0x2000000\0"		\
>  	"console=ttyAMA0,38400n8\0"

I didn't get a respond to my question for v1. How is kernel_size variable used?

York

[U-Boot] [PATCH 09/22][v2] armv8/ls2085a: Increase the supported kernel size

[Sharma Bhupesh]

Hi York,

Sorry for missing this comment on v1.

> From: Sun York-R58495
> Sent: Thursday, May 28, 2015 9:31 PM
> 
> On 05/28/2015 02:24 AM, Prabhakar Kushwaha wrote:
> > From: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> >
> > Increases the kernel size supported for LS2085A platforms:-
> >  - Update environment variables
> >  - Add ramdisk_size in bootargs env variable
> >  - Define  CONFIG_SYS_BOOTM_LEN to 64MB
> >
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > ---
> > Changes for v2: sending as it is for patch set
> >
> >  include/configs/ls2085a_common.h | 9 ++++++---
> >  include/configs/ls2085aqds.h     | 2 +-
> >  include/configs/ls2085ardb.h     | 2 +-
> >  3 files changed, 8 insertions(+), 5 deletions(-)
> >
> > diff --git a/include/configs/ls2085a_common.h
> b/include/configs/ls2085a_common.h
> > index 749c58d..a33b8a9 100644
> > --- a/include/configs/ls2085a_common.h
> > +++ b/include/configs/ls2085a_common.h
> > @@ -248,13 +248,13 @@ unsigned long long get_qixis_addr(void);
> >  	"initrd_high=0xffffffffffffffff\0"	\
> >  	"kernel_start=0x581200000\0"		\
> >  	"kernel_load=0xa0000000\0"		\
> > -	"kernel_size=0x1000000\0"		\
> > +	"kernel_size=0x2000000\0"		\
> >  	"console=ttyAMA0,38400n8\0"
> 
> I didn't get a respond to my question for v1. How is kernel_size variable
> used?

This variable is used for our default bootcmd to define the kernel size which needs to be copied
from the address pointed by the 'kernel_start' variable to the address pointed to by
the 'kernel_load' variable:

#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"

Regards,
Bhupesh

[U-Boot] [PATCH 09/22][v2] armv8/ls2085a: Increase the supported kernel size

[York Sun]

On 05/28/2015 11:58 AM, Sharma Bhupesh-B45370 wrote:
> Hi York,
> 
> Sorry for missing this comment on v1.
> 
>> From: Sun York-R58495
>> Sent: Thursday, May 28, 2015 9:31 PM
>>
>> On 05/28/2015 02:24 AM, Prabhakar Kushwaha wrote:
>>> From: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>>>
>>> Increases the kernel size supported for LS2085A platforms:-
>>>  - Update environment variables
>>>  - Add ramdisk_size in bootargs env variable
>>>  - Define  CONFIG_SYS_BOOTM_LEN to 64MB
>>>
>>> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>> ---
>>> Changes for v2: sending as it is for patch set
>>>
>>>  include/configs/ls2085a_common.h | 9 ++++++---
>>>  include/configs/ls2085aqds.h     | 2 +-
>>>  include/configs/ls2085ardb.h     | 2 +-
>>>  3 files changed, 8 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/include/configs/ls2085a_common.h
>> b/include/configs/ls2085a_common.h
>>> index 749c58d..a33b8a9 100644
>>> --- a/include/configs/ls2085a_common.h
>>> +++ b/include/configs/ls2085a_common.h
>>> @@ -248,13 +248,13 @@ unsigned long long get_qixis_addr(void);
>>>  	"initrd_high=0xffffffffffffffff\0"	\
>>>  	"kernel_start=0x581200000\0"		\
>>>  	"kernel_load=0xa0000000\0"		\
>>> -	"kernel_size=0x1000000\0"		\
>>> +	"kernel_size=0x2000000\0"		\
>>>  	"console=ttyAMA0,38400n8\0"
>>
>> I didn't get a respond to my question for v1. How is kernel_size variable
>> used?
> 
> This variable is used for our default bootcmd to define the kernel size which needs to be copied
> from the address pointed by the 'kernel_start' variable to the address pointed to by
> the 'kernel_load' variable:
> 
> #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
> 					"$kernel_size && bootm $kernel_load"
> 

Got it. It is just a short-hand for copying images from NOR flash to RAM.

York

[U-Boot] [PATCH 21/22][v2] armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvr

[York Sun]

On 05/28/2015 02:24 AM, Prabhakar Kushwaha wrote:
> From: Stuart Yoder <stuart.yoder@freescale.com>
> 
> The agreed split of the top of memory is 256M for debug server and 256M
> for MC. This patch implements the split.
> 
> In addition, the MC mem must be 512MB aligned, so the amount of memory
> to hide must be 512MB to achieve that alignment.
> 
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Changes for v2: sending as it is for patch set
> 

<snip>

> diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
> index a33b8a9..214d790 100644
> --- a/include/configs/ls2085a_common.h
> +++ b/include/configs/ls2085a_common.h
> @@ -163,21 +163,27 @@ unsigned long long get_qixis_addr(void);
>  #define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
>  
>  /* Debug Server firmware */
> -#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
>  /* 2 sec timeout */
>  #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT			(2 * 1000 * 1000)
>  
>  /* MC firmware */
>  #define CONFIG_FSL_MC_ENET
> -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(512UL * 1024 * 1024)
>  /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
>  #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
>  #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
>  #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
>  #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
>  
> -/* Carve out a DDR region which will not be used by u-boot/Linux */
> +/*
> + * Carve out a DDR region which will not be used by u-boot/Linux
> + *
> + * It will be used by MC and Debug Server. The MC region must be
> + * 512MB aligned, so the min size to hide is 512MB.
> + */
>  #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
> +#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
> +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(256UL * 1024 * 1024)
> +#define CONFIG_SYS_MEM_TOP_HIDE_MIN			(512UL * 1024 * 1024)
>  #define CONFIG_SYS_MEM_TOP_HIDE		get_dram_size_to_hide()

The new macro should be documented.

York

[U-Boot] [PATCH 01/22][v2] armv8/ls2085ardb: Add eth & phy f/w loading support

[York Sun]

On 05/28/2015 02:23 AM, Prabhakar Kushwaha wrote:
> Add support for board eth initialization and support for loading phy
> firmware. PHY firmware needs to be loaded from board_eth_init() because
> all the MACs are not initialized by ldpaa_eth driver.
> 
> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Changes for v2: Sending as it is for patch set
> 

This set (v2) with [21/22 v3] is applied to fsl-qoriq next branch.

York