From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sat, 27 Jun 2015 18:22:17 +0200 Subject: [U-Boot] [PATCH v2 2/8] imx: mx6 correct get_cpu_rev In-Reply-To: <1434018642-16990-2-git-send-email-Peng.Fan@freescale.com> References: <1434018642-16990-1-git-send-email-Peng.Fan@freescale.com> <1434018642-16990-2-git-send-email-Peng.Fan@freescale.com> Message-ID: <558ECDB9.9080904@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/06/2015 12:30, Peng Fan wrote: > The DIGPROG register map: > 23 ------- 16 | 15 ------ 8 | 7 --- 0 | > Major upper | Major Lower | Minor | > > We also need to account for Major Lower. > > Signed-off-by: Ye.Li > Signed-off-by: Peng Fan > --- > > Changes v2: > split from PATCH v1 2/8. This piece code should be in a single patch. > > arch/arm/cpu/armv7/mx6/soc.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index b21bd03..29de624 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) > struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; > u32 reg = readl(&anatop->digprog_sololite); > u32 type = ((reg >> 16) & 0xff); > + u32 major; > > if (type != MXC_CPU_MX6SL) { > reg = readl(&anatop->digprog); > @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) > } > > } > + major = ((reg >> 8) & 0xff); > reg &= 0xff; /* mx6 silicon revision */ > - return (type << 12) | (reg + 0x10); > + return (type << 12) | (reg + (0x10 * (major + 1))); > } > > /* > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================