* [U-Boot] [PATCH 1/3] sunxi:Added NAND Flash defines and MMC2 IO defines for sun6i
2015-06-29 9:47 [U-Boot] [PATCH 1/3] sunxi:Added NAND Flash defines and MMC2 IO defines for sun6i =?gb18030?B?vNPM2Ly8tcTQpMzYu/k=?=
@ 2015-07-05 19:11 ` Hans de Goede
0 siblings, 0 replies; 2+ messages in thread
From: Hans de Goede @ 2015-07-05 19:11 UTC (permalink / raw)
To: u-boot
Hi,
First of all thanks for the patches.
I've a question about this series in general, this series is
for the Mele i7 board, correct?
AFAIK that board has regular NAND, not an eMMC.
It seems your version has an eMMC though, so it seems that
there are 2 versions of the board. Are you sure you have
an I7 and not some other Mele model?
Either way please create a new dts file and defconfig
for your board with emmc, if it really is an I7 use
Mele_I7_eMMC_defconfig as defconfig file name, and
sun6i-a31-mele-i7-emmc.dts as dts filename.
I've added some further comments to these patches inline.
On 29-06-15 11:47, ??????? wrote:
> From 5c6f29ec1882c9f87c6e789e0ae06a974f6c32e0 Mon Sep 17 00:00:00 2001
> From: Zhi Yuan Wan <dv.xw@qq.com>
> Date: Thu, 25 Jun 2015 19:59:39 +0800
> Subject: [PATCH 1/3] sunxi:Added NAND Flash defines and MMC2 IO defines for sun6i
> Signed-off-by: Zhi Yuan Wan <dv.xw@qq.com>
>
> ---
> arch/arm/dts/sun6i-a31.dtsi | 85 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
>
> diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi
> index 008047a..a9100b9 100644
> --- a/arch/arm/dts/sun6i-a31.dtsi
> +++ b/arch/arm/dts/sun6i-a31.dtsi
Please submit dts file patches to the upstream linux kernel
first, using the standard kernel patch submission process.
> @@ -306,6 +306,14 @@
> "apb2_uart4", "apb2_uart5";
> };
>
> + nand_clk: clk at 01c20080 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20080 0x4>;
> + clocks = <&osc24M>, <&pll6 1>;
> + clock-output-names = "nand";
> + };
> +
> mmc0_clk: clk at 01c20088 {
> #clock-cells = <1>;
> compatible = "allwinner,sun4i-a10-mmc-clk";
>
You are only making nand related additions here, yet your
subject talks about mmc2 io-defines, please fix your
commit message to not mention the mmc2 io-defines.
> @@ -427,6 +435,17 @@
> #size-cells = <1>;
> ranges;
>
> + nfc: nand at 01c03000 {
> + compatible = "allwinner,sunxi-nand";
This is wrong, the correct compatible would be:
"allwinner,sun4i-a10-nand" have you tested this at all ?
Since you say you've a board with eMMC I believe this is
untested. Please do not submit untested changes.
If you are not using the nand bits, please drop this patch
from your patchset.
> + reg = <0x01c03000 0x1000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ahb1_gates 13>, <&nand_clk>;
> + clock-names = "ahb", "mod";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> dma: dma-controller at 01c02000 {
> compatible = "allwinner,sun6i-a31-dma";
> reg = <0x01c02000 0x1000>;
> @@ -647,6 +666,14 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> + mmc2_pins_a: mmc2 at 0 {
> + allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> + "PC10", "PC11";
> + allwinner,function = "mmc2";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> gmac_pins_mii_a: gmac_mii at 0 {
> allwinner,pins = "PA0", "PA1", "PA2", "PA3",
> "PA8", "PA9", "PA11",
> @@ -688,6 +715,59 @@
> allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
> +
> + nand_pins_a: nand_base0 at 0 {
> + allwinner,pins = "PC0", "PC1", "PC2",
> + "PC5", "PC8", "PC9", "PC10",
> + "PC11", "PC12", "PC13", "PC14",
> + "PC15", "PC16";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_cs0_pins_a: nand_cs at 0 {
> + allwinner,pins = "PC4";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_cs1_pins_a: nand_cs at 1 {
> + allwinner,pins = "PC3";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_cs2_pins_a: nand_cs at 2 {
> + allwinner,pins = "PC25";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_cs3_pins_a: nand_cs at 3 {
> + allwinner,pins = "PC26";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_rb0_pins_a: nand_rb at 0 {
> + allwinner,pins = "PC6";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_rb1_pins_a: nand_rb at 1 {
> + allwinner,pins = "PC7";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> };
>
> ahb1_rst: reset at 01c202c0 {
> @@ -948,6 +1028,11 @@
> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + sid: eeprom at 01c23800 {
> + compatible = "allwinner,sun6i-a31-sid";
> + reg = <0x01c23800 0x200>;
> + };
> +
> nmi_intc: interrupt-controller at 01f00c0c {
> compatible = "allwinner,sun6i-a31-sc-nmi";
> interrupt-controller;
>
This addition of the sid node is completely unrelated to the
other changes on this commit.
Also this is wrong, the A31 does not have a SID, contrary
to what the datasheets say there is nothing at address
1c23800.
Please drop this part of this patch.
Regards,
Hans
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