[U-Boot] [PATCH 10/13] mtd/nand/tegra: alignment workaround

Simon Glass
2015-07-06T16:38:56Z

Hi Marcel,

On 6 July 2015 at 02:20, Marcel Ziswiler <marcel@ziswiler.com> wrote:
> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
>
> Introduce cache alignment bounce buffer to workaround issues as follows:
>
> Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
> ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
> ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
> Done
> Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ]
>
> Starting kernel ...
>
> undefined instruction
> pc : [<005ff03c>] lr : [<0000800c>]
> sp : 0144b6e8 ip : 01000188 fp : 0144a6c8
> r10: 00000000 r9 : 411fc090 r8 : 00000100
> r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000
> r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000
> Flags: nZCv IRQs off FIQs off Mode SVC_32
> Resetting CPU ...
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> ---
> drivers/mtd/nand/tegra_nand.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)

Can you use the existing bouncebuf for this?

Regards,
Simon