From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Fri, 10 Jul 2015 09:56:23 +0200 Subject: [U-Boot] [PATCH] mmc:fsl_esdhc invalidate dcache before read In-Reply-To: <1435199546-12292-1-git-send-email-Peng.Fan@freescale.com> References: <1435199546-12292-1-git-send-email-Peng.Fan@freescale.com> Message-ID: <559F7AA7.4030003@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Peng, I see this patch is now delegated to me. Then, I have no objections to merge it into u-boot-imx if Pantelis agree. On 25/06/2015 04:32, Peng Fan wrote: > DCIMVAC is upgraded to DCCIMVAC for the individual processor > (Cortex-A7) that the DCIMVAC is executed on. > Can you better explain it ? What are the consequences of using DCCIMVAC into this driver ? This driver is not only for i.MX. It runs on PowerPc, too. Do you tested this patch on PowerPC architecture, too ? Maybe someone else can do it ? > We should follow the linux dma follow. Before DMA read, first > invalidate dcache then after DMA read, invalidate dcache again. > > With the DMA direction DMA_FROM_DEVICE, the dcache need be > invalidated again after the DMA completion. The reason is > that we need explicity make sure the dcache been invalidated > thus to get the DMA'ed memory correctly from the physical memory. > Any cache-line fill during the DMA operations such as the > pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. > > Signed-off-by: Peng Fan > Signed-off-by: Ye.Li > Signed-off-by: Nitin Garg > Signed-off-by: Jason Liu > --- > drivers/mmc/fsl_esdhc.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index c4719e6..0510bf0 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) > err = esdhc_setup_data(mmc, data); > if(err) > return err; > + > + if (data->flags & MMC_DATA_READ) > + check_and_invalidate_dcache_range(cmd, data); > } > > /* Figure out the transfer arguments */ > @@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) > } > } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); > > + /* > + * Need invalidate the dcache here again to avoid any > + * cache-fill during the DMA operations such as the > + * speculative pre-fetching etc. > + */ > if (data->flags & MMC_DATA_READ) > check_and_invalidate_dcache_range(cmd, data); > #endif > >From my side it is ok. Reviewed-by: Stefano Babic Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================