From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Thu, 16 Jul 2015 08:46:24 +0200 Subject: [U-Boot] [PATCH RESEND 0/7] spi: cadence_qspi: optimize & fix indirect rd-writes In-Reply-To: <9026814FBF99304F9FA3AC3FB72F3E2F02961958@SAFEX1MAIL4.st.com> References: <1434507265-16573-1-git-send-email-vikas.manocha@st.com> <5582B342.20209@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F016A86FC@SAFEX1MAIL4.st.com> <5583B3A1.9070602@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F016A8757@SAFEX1MAIL4.st.com> <5587C89A.6050209@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F02961452@SAFEX1MAIL4.st.com> <55A37E32.2000907@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F02961958@SAFEX1MAIL4.st.com> Message-ID: <55A75340.80509@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Vikas, On 15.07.2015 23:14, Vikas MANOCHA wrote: >>> In addition can you please check the patch causing this instability on >>> socfpga. I don't like to bug you but to close this patchset, this info >>> & tests mentioned above seems to be required. >> >> Okay. I'll try to find some time this week to do some testing here. It seems >> that the other cadence patchset from you ([v4 00/10] spi: >> cadence_qspi: sram depth from DT & fix for FIFO width) is not pulled into >> mainline yet. To make it easier for me, could you perhaps publish a git >> repository that is based on current mainline. And has the mentioned above >> patch series included. And all the patches in the latest version that are >> currently causing these problems on SoCFPGA? > > The patchset was in u-boot-spi repository, yesterday pulled by Tom in mainline. I will rebase the patchset in discussion > (spi: cadence_qspi: optimize & fix indirect rd-writes) on mainline master & send the V2. > > Let me know if it is ok. Okay, I'll try to find some time later this week or next week for some tests. Thanks, Stefan