[U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

[Dinh Nguyen <dinguyen@opensource.altera.com>]

On 7/20/15 1:36 PM, Marek Vasut wrote:
> On Monday, July 20, 2015 at 03:40:00 PM, Dinh Nguyen wrote:
>> On 7/17/15 3:22 PM, Marek Vasut wrote:
>>> On Friday, July 17, 2015 at 09:58:20 PM, Dinh Nguyen wrote:
>>>> On 07/12/2015 02:50 PM, Marek Vasut wrote:
>>>>> On Friday, June 26, 2015 at 10:01:47 PM, Marek Vasut wrote:
>>>>>> On Friday, June 26, 2015 at 06:43:13 PM, Marek Vasut wrote:
>>>>>>> On Wednesday, June 03, 2015 at 05:52:47 AM,
>>>>>>> dinguyen at opensource.altera.com
>>>>>>>
>>>>>>> wrote:
>>>>>>>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>> This is v4 of the patch series that adds the DDR controller driver
>>>>>>>> for Altera's SoCFPGA platform.
>>>>>>>>
>>>>>>>> v4:
>>>>>>>> - Further cleanup by removing comments that do not apply for
>>>>>>>> Cyclone5. - Removed more unused functions
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>
>>>>>>> I applied this to u-boot/master and tried building for
>>>>>>> socfpga_cyclone5, this is what I'm getting after I fixed these
>>>>>>> patches to actually apply to u-boot/master (there was a minor
>>>>>>> conflict in Makefile):
>>>>>>>
>>>>>>> drivers/ddr/altera/sdram.c:11:35: fatal error:
>>>>>>> asm/arch/sdram_config.h: No such file or directory
>>>>>>>
>>>>>>>  #include <asm/arch/sdram_config.h>
>>>>>>
>>>>>> OK, these files were misplaced by the patch. Now I got it to compile,
>>>>>> only to see that when I try to init DRAM on sockit using those, PHY
>>>>>> calibration fails (run_mem_calibrate() returns 1).
>>>>>>
>>>>>> btw. I also think sdram_config.h should go into board/altera/ instead
>>>>>> .
>>>>>
>>>>> Just a quick heads-up, I'm cleaning this and the SPL up. I got SoCkit
>>>>> booting from SD/MMC and I'm over 50 patches now. I'll submit them when
>>>>> I'm done with this. I'd like to avoid merge conflicts now, so please
>>>>> wait for my submission if possible.
>>>>
>>>> So you want me to wait regarding the SDRAM patches?
>>>
>>> Hi,
>>>
>>> yeah, I have some insane amount of cleanup patches and fixes already. I
>>> will post them once I'm done. What I am sorely missing is the UniPHY
>>> register interface documentation, it looks like that is not public, so
>>> I don't exactly know if what sequencer.c does is really correct.
>>> Sometimes I have serious doubts about that too . Can you give me the
>>> documentation please ?
>>
>> Have you seen this link[1]?
> 
> Yes, but that is by far not all of the registers used in the sequencer.c,
> is it ?
> 

Looks like it's in the entire emi.pdf file[1]. Please look at volume 3,
or page 531 of 895. The section for the UniPHY.

Dinh
[1]
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/external-memory/emi.pdf