[U-Boot] [PATCHv4 0/3] drivers/ddr/altera: Add the DDR controller driver for SoCFPGA

[Dinh Nguyen <dinguyen@opensource.altera.com>]

On 7/20/15 2:40 PM, Marek Vasut wrote:
> On Monday, July 20, 2015 at 09:31:39 PM, Dinh Nguyen wrote:
> [...]
>>>>> Hi,
>>>>>
>>>>> yeah, I have some insane amount of cleanup patches and fixes already. I
>>>>> will post them once I'm done. What I am sorely missing is the UniPHY
>>>>> register interface documentation, it looks like that is not public, so
>>>>> I don't exactly know if what sequencer.c does is really correct.
>>>>> Sometimes I have serious doubts about that too . Can you give me the
>>>>> documentation please ?
>>>>
>>>> Have you seen this link[1]?
>>>
>>> Yes, but that is by far not all of the registers used in the sequencer.c,
>>> is it ?
>>
>> Looks like it's in the entire emi.pdf file[1]. Please look at volume 3,
>> or page 531 of 895. The section for the UniPHY.
> 
> I extracted all the possible addresses used in the sequencer while cleaning
> it up, they're below. I cannot find these in any documentation. I checked the
> EMI RM, sure, but there seems to be many more registers all around the place
> than what are described in the EMI RM. Any ideas please ? Maybe this is not
> even the UniPHY anymore ?

What I've been told was that the UniPHY was not really properly
documented, and that when anyone needed to modify the registers, they
would have to go back to the RTL to figure out exactly what's going on.

So I've only been able to get the following information on the registers
below:

[Read/Write manager - this is a small accelerator that can be programmed
with custom microcode to "play" sequences of commands to the memory
interface at memory speeds]

[This register will execute a specific RW MGR command for a single DQS
group]
9 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET          0x0
[This register will execute a specific RW MGR command for all DQS groups
in the memory in parallel]
 20 #define RW_MGR_RUN_ALL_GROUPS_OFFSET            0x0400
[Resets the read datapath to clear out any corrupted data]
 21 #define RW_MGR_RESET_READ_DATAPATH_OFFSET       0x1000
[Configurable mask to specify which chip select should be asserted and
what the value of ODT should be when CS is asserted]
 22 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET       0x1400
[Write pointer into the instruction microcode rom]
 23 #define RW_MGR_INST_ROM_WRITE_OFFSET            0x1800
[Write pointer into the address ROM that is indexed via instruction
microcode]
 24 #define RW_MGR_AC_ROM_WRITE_OFFSET              0x1C00

[The Scan-Chain Control manager is a piece of hardware that interfaces
to the serial scan chain configuration bus of the PHY.  It is used to
program and modify delay values during calibration and sometimes during
operation for things like DQS tracking]
[which DQS group the SCC_MGR is talking to]
 80 #define SCC_MGR_GROUP_COUNTER_OFFSET            0x0000
[Offset for DQS input delay]
 81 #define SCC_MGR_DQS_IN_DELAY_OFFSET             0x0100
[Offset for DQS Enable Coarse input Phase register]
 82 #define SCC_MGR_DQS_EN_PHASE_OFFSET             0x0200
[Offset for DQS Enable Phase fine-grained delay]
 83 #define SCC_MGR_DQS_EN_DELAY_OFFSET             0x0300
[Offset for DQ/DQS coarse output phase register]
 84 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET          0x0400
[Offset for termination control delay setting register]
 85 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET           0x0500
[Don't know]
 86 #define SCC_MGR_IO_OUT1_DELAY_OFFSET            0x0700
[Input delay register]
 87 #define SCC_MGR_IO_IN_DELAY_OFFSET              0x0900

[It seems these are added specifically for 28nm handshaking with HPS
only.  I'm strictly guessing here]
[DQS enable gating delay register]
 90 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET        0x0600
[Output enable timing register]
 91 #define SCC_MGR_IO_OE_DELAY_OFFSET              0x0800
[Not sure]
 92 #define SCC_MGR_HHP_GLOBALS_OFFSET              0x0A00
[Not sure]
 93 #define SCC_MGR_HHP_RFILE_OFFSET                0x0B00
[Probably a register to query whether or not the AFI bus is still in
calibration mode or if the HPS has control]
 94 #define SCC_MGR_AFI_CAL_INIT_OFFSET             0x0D00
 95


Dinh