[U-Boot] [PATCH 0/8] ARM: keystone2: Clocls and PLLs cleanup

[U-Boot] [PATCH 0/8] ARM: keystone2: Clocls and PLLs cleanup

[Lokesh Vutla]

This seires does a several bunch of cleanups for clock and PLL
related definitions. This helps a lot in adding data for
new Keystone2 SoCs. And also adds support for CPU detection.

This is based on Nishanth's config cleanup series:
https://www.mail-archive.com/u-boot%40lists.denx.de/msg177822.html

Tested on K2HK-evm: http://pastebin.ubuntu.com/11920541/

Lokesh Vutla (8):
  ARM: keystone2: Cleanup SoC detection
  ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO
  ARM: keystone2: Cleanup PLL init code
  ARM: keystone2: Fix dev and arm speed detection
  ARM: keystone2: Use common address for PLL
  ARM: keystone2: Cleanup pll calling
  ARM: keystone2: Remove unsed externalk clocks
  ARM: keystone2: Use common definition for clk_get_rate

 arch/arm/mach-keystone/Makefile                    |   3 -
 arch/arm/mach-keystone/clock-k2e.c                 | 117 -----
 arch/arm/mach-keystone/clock-k2hk.c                | 145 ------
 arch/arm/mach-keystone/clock-k2l.c                 | 138 ------
 arch/arm/mach-keystone/clock.c                     | 527 +++++++++++++--------
 arch/arm/mach-keystone/cmd_clock.c                 |   7 +-
 arch/arm/mach-keystone/include/mach/clock-k2e.h    |  58 +--
 arch/arm/mach-keystone/include/mach/clock-k2hk.h   |  64 +--
 arch/arm/mach-keystone/include/mach/clock-k2l.h    |  59 +--
 arch/arm/mach-keystone/include/mach/clock.h        |  60 ++-
 arch/arm/mach-keystone/include/mach/clock_defs.h   | 107 +++--
 .../arm/mach-keystone/include/mach/hardware-k2hk.h |   4 -
 arch/arm/mach-keystone/include/mach/hardware.h     |  51 +-
 arch/arm/mach-keystone/init.c                      |  24 +
 board/ti/ks2_evm/board.c                           |   1 -
 board/ti/ks2_evm/board_k2e.c                       |  41 +-
 board/ti/ks2_evm/board_k2hk.c                      |  47 +-
 board/ti/ks2_evm/board_k2l.c                       |  46 +-
 include/configs/ti_armv7_keystone2.h               |   1 +
 19 files changed, 603 insertions(+), 897 deletions(-)
 delete mode 100644 arch/arm/mach-keystone/clock-k2e.c
 delete mode 100644 arch/arm/mach-keystone/clock-k2hk.c
 delete mode 100644 arch/arm/mach-keystone/clock-k2l.c

-- 
2.1.4

[U-Boot] [PATCH 1/8] ARM: keystone2: Cleanup SoC detection

[Lokesh Vutla]

Add proper register definition for JTAG ID and
cleanup cpu_is_* functions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/include/mach/hardware.h | 42 ++++++++++++++++----------
 1 file changed, 26 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 16cbcee..15c25b1 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -237,6 +237,17 @@ typedef volatile unsigned int   *dv_reg_p;
 /* SGMII SerDes */
 #define KS2_SGMII_SERDES_BASE		0x0232a000
 
+/* JTAG ID register */
+#define JTAGID_VARIANT_SHIFT	28
+#define JTAGID_VARIANT_MASK	(0xf << 28)
+#define JTAGID_PART_NUM_SHIFT	12
+#define JTAGID_PART_NUM_MASK	(0xffff << 12)
+
+/* PART NUMBER definitions */
+#define CPU_66AK2Hx	0xb981
+#define CPU_66AK2Ex	0xb9a6
+#define CPU_66AK2Lx	0xb9a7
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
@@ -250,34 +261,33 @@ typedef volatile unsigned int   *dv_reg_p;
 #endif
 
 #ifndef __ASSEMBLY__
-static inline int cpu_is_k2hk(void)
+
+static inline u16 get_part_number(void)
 {
-	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
+	u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
 
-	return (part_no == 0xb981) ? 1 : 0;
+	return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
 }
 
-static inline int cpu_is_k2e(void)
+static inline u8 cpu_is_k2hk(void)
 {
-	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
-
-	return (part_no == 0xb9a6) ? 1 : 0;
+	return get_part_number() == CPU_66AK2Hx;
 }
 
-static inline int cpu_is_k2l(void)
+static inline u8 cpu_is_k2e(void)
 {
-	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
+	return get_part_number() == CPU_66AK2Ex;
+}
 
-	return (part_no == 0xb9a7) ? 1 : 0;
+static inline u8 cpu_is_k2l(void)
+{
+	return get_part_number() == CPU_66AK2Lx;
 }
 
-static inline int cpu_revision(void)
+static inline u8 cpu_revision(void)
 {
-	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
-	unsigned int rev	= (jtag_id >> 28) & 0xf;
+	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
+	u8 rev	= (jtag_id & JTAGID_VARIANT_MASK) & JTAGID_VARIANT_SHIFT;
 
 	return rev;
 }
-- 
2.1.4

[U-Boot] [PATCH 1/8] ARM: keystone2: Cleanup SoC detection

[Vitaly Andrianov]

On 07/22/2015 11:39 AM, Lokesh Vutla wrote:
> Add proper register definition for JTAG ID and
> cleanup cpu_is_* functions.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>   arch/arm/mach-keystone/include/mach/hardware.h | 42 ++++++++++++++++----------
>   1 file changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
> index 16cbcee..15c25b1 100644
> --- a/arch/arm/mach-keystone/include/mach/hardware.h
> +++ b/arch/arm/mach-keystone/include/mach/hardware.h
> @@ -237,6 +237,17 @@ typedef volatile unsigned int   *dv_reg_p;
>   /* SGMII SerDes */
>   #define KS2_SGMII_SERDES_BASE		0x0232a000
>
> +/* JTAG ID register */
> +#define JTAGID_VARIANT_SHIFT	28
> +#define JTAGID_VARIANT_MASK	(0xf << 28)
> +#define JTAGID_PART_NUM_SHIFT	12
> +#define JTAGID_PART_NUM_MASK	(0xffff << 12)
> +
> +/* PART NUMBER definitions */
> +#define CPU_66AK2Hx	0xb981
> +#define CPU_66AK2Ex	0xb9a6
> +#define CPU_66AK2Lx	0xb9a7
> +
>   #ifdef CONFIG_SOC_K2HK
>   #include <asm/arch/hardware-k2hk.h>
>   #endif
> @@ -250,34 +261,33 @@ typedef volatile unsigned int   *dv_reg_p;
>   #endif
>
>   #ifndef __ASSEMBLY__
> -static inline int cpu_is_k2hk(void)
> +
> +static inline u16 get_part_number(void)
>   {
> -	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
> -	unsigned int part_no	= (jtag_id >> 12) & 0xffff;
> +	u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
>
> -	return (part_no == 0xb981) ? 1 : 0;
> +	return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
>   }
>
> -static inline int cpu_is_k2e(void)
> +static inline u8 cpu_is_k2hk(void)
>   {
> -	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
> -	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
> -
> -	return (part_no == 0xb9a6) ? 1 : 0;
> +	return get_part_number() == CPU_66AK2Hx;
>   }
>
> -static inline int cpu_is_k2l(void)
> +static inline u8 cpu_is_k2e(void)
>   {
> -	unsigned int jtag_id    = __raw_readl(KS2_JTAG_ID_REG);
> -	unsigned int part_no    = (jtag_id >> 12) & 0xffff;
> +	return get_part_number() == CPU_66AK2Ex;
> +}
>
> -	return (part_no == 0xb9a7) ? 1 : 0;
> +static inline u8 cpu_is_k2l(void)
> +{
> +	return get_part_number() == CPU_66AK2Lx;
>   }
>
> -static inline int cpu_revision(void)
> +static inline u8 cpu_revision(void)
>   {
> -	unsigned int jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
> -	unsigned int rev	= (jtag_id >> 28) & 0xf;
> +	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
> +	u8 rev	= (jtag_id & JTAGID_VARIANT_MASK) & JTAGID_VARIANT_SHIFT;
>
>   	return rev;
>   }
>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>

[U-Boot] [PATCH 1/8] ARM: keystone2: Cleanup SoC detection

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:11PM +0530, Lokesh Vutla wrote:

> Add proper register definition for JTAG ID and
> cleanup cpu_is_* functions.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 1/8] ARM: keystone2: Cleanup SoC detection

[Lokesh Vutla]

On Friday 24 July 2015 12:59 AM, Tom Rini wrote:
> On Wed, Jul 22, 2015 at 09:09:11PM +0530, Lokesh Vutla wrote:
>
>> Add proper register definition for JTAG ID and
>> cleanup cpu_is_* functions.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Thanks for the review Tom.
Vitaly has some comments. Ill repost this
series with Vitaly's comments addressed.

Thanks and regards,
Lokesh
>

[U-Boot] [PATCH 2/8] ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO

[Lokesh Vutla]

Add print_cpuinfo() function and enable
CONFIG_DISPLAY_CPUINFO for keystone platforms,
so that cpu info can be displayed during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/init.c        | 24 ++++++++++++++++++++++++
 include/configs/ti_armv7_keystone2.h |  1 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index c96845c..d742ad3 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -149,3 +149,27 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u16 cpu = get_part_number();
+
+	puts("CPU: ");
+	switch (cpu) {
+	case CPU_66AK2Hx:
+		puts("66AK2Hx\n");
+		break;
+	case CPU_66AK2Lx:
+		puts("66AK2Lx\n");
+		break;
+	case CPU_66AK2Ex:
+		puts("66AK2Ex\n");
+		break;
+	default:
+		puts("Unknown\n");
+	}
+
+	return 0;
+}
+#endif
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 198e365..056b938 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -15,6 +15,7 @@
 /* U-Boot Build Configuration */
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
 
 /* SoC Configuration */
 #define CONFIG_ARCH_CPU_INIT
-- 
2.1.4

[U-Boot] [PATCH 2/8] ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO

[Vitaly Andrianov]

On 07/22/2015 11:39 AM, Lokesh Vutla wrote:
> Add print_cpuinfo() function and enable
> CONFIG_DISPLAY_CPUINFO for keystone platforms,
> so that cpu info can be displayed during boot.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>   arch/arm/mach-keystone/init.c        | 24 ++++++++++++++++++++++++
>   include/configs/ti_armv7_keystone2.h |  1 +
>   2 files changed, 25 insertions(+)
>
> diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
> index c96845c..d742ad3 100644
> --- a/arch/arm/mach-keystone/init.c
> +++ b/arch/arm/mach-keystone/init.c
> @@ -149,3 +149,27 @@ void enable_caches(void)
>   	dcache_enable();
>   #endif
>   }
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> +	u16 cpu = get_part_number();
> +
> +	puts("CPU: ");
> +	switch (cpu) {
> +	case CPU_66AK2Hx:
> +		puts("66AK2Hx\n");
> +		break;
> +	case CPU_66AK2Lx:
> +		puts("66AK2Lx\n");
> +		break;
> +	case CPU_66AK2Ex:
> +		puts("66AK2Ex\n");
> +		break;
> +	default:
> +		puts("Unknown\n");
> +	}
> +
> +	return 0;
> +}
> +#endif
> diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
> index 198e365..056b938 100644
> --- a/include/configs/ti_armv7_keystone2.h
> +++ b/include/configs/ti_armv7_keystone2.h
> @@ -15,6 +15,7 @@
>   /* U-Boot Build Configuration */
>   #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
>   #define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_DISPLAY_CPUINFO
>
>   /* SoC Configuration */
>   #define CONFIG_ARCH_CPU_INIT
>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>

[U-Boot] [PATCH 2/8] ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:12PM +0530, Lokesh Vutla wrote:

> Add print_cpuinfo() function and enable
> CONFIG_DISPLAY_CPUINFO for keystone platforms,
> so that cpu info can be displayed during boot.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 3/8] ARM: keystone2: Cleanup PLL init code

[Lokesh Vutla]

There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock.c                   | 309 ++++++++++-------------
 arch/arm/mach-keystone/include/mach/clock-k2e.h  |   1 +
 arch/arm/mach-keystone/include/mach/clock.h      |   1 -
 arch/arm/mach-keystone/include/mach/clock_defs.h |  77 +++++-
 board/ti/ks2_evm/board.c                         |   1 -
 5 files changed, 201 insertions(+), 188 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 625907f..d8311ca 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -18,195 +18,157 @@ static void wait_for_completion(const struct pll_init_data *data)
 	int i;
 	for (i = 0; i < 100; i++) {
 		sdelay(450);
-		if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
+		if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
 			break;
 	}
 }
 
-void init_pll(const struct pll_init_data *data)
+static inline void bypass_main_pll(const struct pll_init_data *data)
+{
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
+			   PLLCTL_PLLEN_MASK);
+
+	/* 4 cycles of reference clock CLKIN*/
+	sdelay(340);
+}
+
+static void configure_mult_div(const struct pll_init_data *data)
 {
-	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
+	u32 pllm, plld, bwadj;
 
 	pllm = data->pll_m - 1;
-	plld = (data->pll_d - 1) & PLL_DIV_MASK;
-	pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
+	plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
 
-	if (data->pll == MAIN_PLL) {
-		/* The requered delay before main PLL configuration */
-		sdelay(210000);
+	/* Program Multiplier */
+	if (data->pll == MAIN_PLL)
+		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
 
-		tmp = pllctl_reg_read(data->pll, secctl);
+	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+			CFG_PLLCTL0_PLLM_MASK,
+			pllm << CFG_PLLCTL0_PLLM_SHIFT);
+
+	/* Program BWADJ */
+	bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
+	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+			CFG_PLLCTL0_BWADJ_MASK,
+			(bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
+			CFG_PLLCTL0_BWADJ_MASK);
+	bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
+	clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
+			CFG_PLLCTL1_BWADJ_MASK, bwadj);
+
+	/* Program Divider */
+	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+			CFG_PLLCTL0_PLLD_MASK, plld);
+}
 
-		if (tmp & (PLLCTL_BYPASS)) {
-			setbits_le32(keystone_pll_regs[data->pll].reg1,
-				     BIT(MAIN_ENSAT_OFFSET));
+void configure_main_pll(const struct pll_init_data *data)
+{
+	u32 tmp, pllod;
 
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
-					   PLLCTL_PLLENSRC);
-			sdelay(340);
+	pllod = data->pll_od - 1;
 
-			pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
-			pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-			sdelay(21000);
+	/* 100 micro sec for stabilization */
+	sdelay(210000);
 
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-		} else {
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
-					   PLLCTL_PLLENSRC);
-			sdelay(340);
-		}
+	tmp = pllctl_reg_read(data->pll, secctl);
 
-		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
+	/* Check for Bypass */
+	if (tmp & SECCTL_BYPASS_MASK) {
+		setbits_le32(keystone_pll_regs[data->pll].reg1,
+			     CFG_PLLCTL1_ENSAT_MASK);
 
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLLM_MULT_HI_SMASK, (pllm << 6));
-
-		/* Set the BWADJ     (12 bit field)  */
-		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLL_BWADJ_LO_SMASK,
-				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
-				PLL_BWADJ_HI_MASK,
-				(tmp_ctl >> 8));
-
-		/*
-		 * Set the pll divider (6 bit field) *
-		 * PLLD[5:0] is located in MAINPLLCTL0
-		 */
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLL_DIV_MASK, plld);
-
-		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
-		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
-			       (pllod << PLL_CLKOD_SHIFT));
-		wait_for_completion(data);
-
-		pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
-		pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
-		pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
-		pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
-		pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
-
-		pllctl_reg_setbits(data->pll, alnctl, 0x1f);
-
-		/*
-		 * Set GOSET bit in PLLCMD to initiate the GO operation
-		 * to change the divide
-		 */
-		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
-		sdelay(1500); /* wait for the phase adj */
-		wait_for_completion(data);
-
-		/* Reset PLL */
-		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
-		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-		sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */
-
-		pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
-
-		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+		bypass_main_pll(data);
 
-#ifndef CONFIG_SOC_K2E
-	} else if (data->pll == TETRIS_PLL) {
-		bwadj = pllm >> 1;
-		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
-		setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
-		/*
-		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
-		 * only applicable for Kepler
-		 */
-		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
-		setbits_le32(keystone_pll_regs[data->pll].reg1 ,
-			     PLL_PLLRST | PLLCTL_ENSAT);
-
-		/*
-		 * 3 Program PLLM and PLLD in PLLCTL0 register
-		 * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
-		 * PLLCTL1 register. BWADJ value must be set
-		 * to ((PLLM + 1) >> 1) ? 1)
-		 */
-		tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
-			(pllm << 6) |
-			(plld & PLL_DIV_MASK) |
-			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
-		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
-		tmp &= ~(PLL_BWADJ_HI_MASK);
-		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-		/*
-		 * 5 Wait for at least 5 us based on the reference
-		 * clock (PLL reset time)
-		 */
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
-
-		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
-		clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
-		/*
-		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
-		 * (PLL lock time)
-		 */
-		sdelay(105000);
-		/* 8 disable bypass */
-		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
-		/*
-		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
-		 * only applicable for Kepler
-		 */
-		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
-	} else {
-		setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
-		/*
-		 * process keeps state of Bypass bit while programming
-		 * all other DDR PLL settings
-		 */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
-		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
-
-		/*
-		 * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
-		 * bypass disabled
-		 */
-		bwadj = pllm >> 1;
-		tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
-			(pllm << PLL_MULT_SHIFT) |
-			(plld & PLL_DIV_MASK) |
-			(pllod << PLL_CLKOD_SHIFT);
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
-		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
-		tmp &= ~(PLL_BWADJ_HI_MASK);
-		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
-
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-
-		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
-		tmp = PLL_PLLRST;
-		/* Set RESET bit = 1 */
-		setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
-		/* Wait for a minimum of 7 us*/
+		/* Powerdown and powerup Main Pll */
+		pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+		/* 5 micro sec */
 		sdelay(21000);
-		/* Clear RESET bit */
-		clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
-		sdelay(105000);
 
-		/* clear BYPASS (Enable PLL Mode) */
-		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
+		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
+	} else {
+		bypass_main_pll(data);
 	}
 
+	configure_mult_div(data);
+
+	/* Program Output Divider */
+	pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
+		       ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
+
+	/* Program PLLDIVn */
+	wait_for_completion(data);
+	pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
+	pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
+	pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
+	pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
+	pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
+	pllctl_reg_setbits(data->pll, alnctl, ALNCTL_ALN5_MASK);
 	/*
-	 * This is required to provide a delay between multiple
-	 * consequent PPL configurations
+	 * Set GOSET bit in PLLCMD to initiate the GO operation
+	 * to change the divide
 	 */
-	sdelay(210000);
+	pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
+	wait_for_completion(data);
+
+	/* Reset PLL */
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+	sdelay(21000);	/* Wait for a minimum of 7 us*/
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
+	sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */
+
+	/* Enable PLL */
+	pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
+}
+
+void configure_secondary_pll(const struct pll_init_data *data)
+{
+	int pllod = data->pll_od - 1;
+
+	/* Enable Bypass mode */
+	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
+	setbits_le32(keystone_pll_regs[data->pll].reg0,
+		     CFG_PLLCTL0_BYPASS_MASK);
+
+	configure_mult_div(data);
+
+	/* Program Output Divider */
+	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
+			CFG_PLLCTL0_CLKOD_MASK,
+			(pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
+			CFG_PLLCTL0_CLKOD_MASK);
+
+	/* Reset PLL */
+	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+	/* Wait for 5 micro seconds */
+	sdelay(21000);
+
+	/* Select the Output of PASS PLL as input to PASS */
+	if (data->pll == PASS_PLL)
+		setbits_le32(keystone_pll_regs[data->pll].reg1,
+			     CFG_PLLCTL1_PAPLL_MASK);
+
+	/* Select the Output of ARM PLL as input to ARM */
+	if (data->pll == TETRIS_PLL)
+		setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
+
+	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
+	/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
+	sdelay(105000);
+
+	/* Switch to PLL mode */
+	clrbits_le32(keystone_pll_regs[data->pll].reg0,
+		     CFG_PLLCTL0_BYPASS_MASK);
+}
+
+void init_pll(const struct pll_init_data *data)
+{
+	if (data->pll == MAIN_PLL)
+		configure_main_pll(data);
+	else
+		configure_secondary_pll(data);
 }
 
 void init_plls(int num_pll, struct pll_init_data *config)
@@ -257,16 +219,3 @@ inline int get_max_dev_speed(void)
 {
 	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
 }
-
-void pass_pll_pa_clk_enable(void)
-{
-	u32 reg;
-
-	reg = readl(keystone_pll_regs[PASS_PLL].reg1);
-
-	reg |= PLLCTL_PAPLL;
-	writel(reg, keystone_pll_regs[PASS_PLL].reg1);
-
-	/* wait till clock is enabled */
-	sdelay(15000);
-}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index d013b83..68e15ac 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -55,6 +55,7 @@ enum pll_type_e {
 	CORE_PLL,
 	PASS_PLL,
 	DDR3_PLL,
+	TETRIS_PLL,
 };
 
 enum {
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 9f6cfb2..7218230 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -58,7 +58,6 @@ void init_pll(const struct pll_init_data *data);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
-void pass_pll_pa_clk_enable(void);
 int get_max_dev_speed(void);
 int get_max_arm_speed(void);
 
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b..ff12689 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -69,7 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
 
 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
 
-/* PLLCTL Bits */
 #define PLLCTL_BYPASS           BIT(23)
 #define PLL_PLLRST              BIT(14)
 #define PLLCTL_PAPLL            BIT(13)
@@ -102,10 +101,76 @@ static struct pllctl_regs *pllctl_regs[] = {
 #define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
 #define PLL_BWADJ_HI_MASK       0xf
 
-#define PLLM_RATIO_DIV1         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV2         (PLLDIV_ENABLE | 0x0)
-#define PLLM_RATIO_DIV3         (PLLDIV_ENABLE | 0x1)
-#define PLLM_RATIO_DIV4         (PLLDIV_ENABLE | 0x4)
-#define PLLM_RATIO_DIV5         (PLLDIV_ENABLE | 0x17)
+/* PLLCTL Bits */
+#define PLLCTL_PLLENSRC_SHIF	5
+#define PLLCTL_PLLENSRC_MASK	BIT(5)
+#define PLLCTL_PLLRST_SHIFT	3
+#define PLLCTL_PLLRST_MASK	BIT(3)
+#define PLLCTL_PLLPWRDN_SHIFT	1
+#define PLLCTL_PLLPWRDN_MASK	BIT(1)
+#define PLLCTL_PLLEN_SHIFT	0
+#define PLLCTL_PLLEN_MASK	BIT(0)
+
+/* SECCTL Bits */
+#define SECCTL_BYPASS_SHIFT	23
+#define SECCTL_BYPASS_MASK	BIT(23)
+#define SECCTL_OP_DIV_SHIFT	19
+#define SECCTL_OP_DIV_MASK	(0xf << 19)
+
+/* PLLM Bits */
+#define PLLM_MULT_LO_SHIFT	0
+#define PLLM_MULT_LO_MASK	0x3f
+#define PLLM_MULT_LO_BITS	6
+
+/* PLLDIVn Bits */
+#define PLLDIV_ENABLE_SHIFT	15
+#define PLLDIV_ENABLE_MASK	BIT(15)
+#define PLLDIV_RATIO_SHIFT	0x0
+#define PLLDIV_RATIO_MASK	0xff
+
+/* PLLCMD Bits */
+#define PLLCMD_GOSET_SHIFT	0
+#define PLLCMD_GOSET_MASK	BIT(0)
+
+/* PLLSTAT Bits */
+#define PLLSTAT_GOSTAT_SHIFT	0
+#define PLLSTAT_GOSTAT_MASK	BIT(0)
+
+/* ALNCTL Bits */
+#define ALNCTL_ALNn_MASK	0xffff
+#define ALNCTL_ALN5_MASK	0x1f
+
+/* Device Config PLLCTL0 */
+#define CFG_PLLCTL0_BWADJ_SHIFT		24
+#define CFG_PLLCTL0_BWADJ_MASK		(0xff << 24)
+#define CFG_PLLCTL0_BWADJ_BITS		8
+#define CFG_PLLCTL0_BYPASS_SHIFT	23
+#define CFG_PLLCTL0_BYPASS_MASK		BIT(23)
+#define CFG_PLLCTL0_CLKOD_SHIFT		19
+#define CFG_PLLCTL0_CLKOD_MASK		(0xf << 19)
+#define CFG_PLLCTL0_PLLM_HI_SHIFT	12
+#define CFG_PLLCTL0_PLLM_HI_MASK	(0x7f << 12)
+#define CFG_PLLCTL0_PLLM_SHIFT		6
+#define CFG_PLLCTL0_PLLM_MASK		(0x1fff << 6)
+#define CFG_PLLCTL0_PLLD_SHIFT		0
+#define CFG_PLLCTL0_PLLD_MASK		0x3f
+
+/* Device Config PLLCTL1 */
+#define CFG_PLLCTL1_RST_SHIFT	14
+#define CFG_PLLCTL1_RST_MASK	BIT(14)
+#define CFG_PLLCTL1_PAPLL_SHIFT	13
+#define CFG_PLLCTL1_PAPLL_MASK	BIT(13)
+#define CFG_PLLCTL1_ENSAT_SHIFT	6
+#define CFG_PLLCTL1_ENSAT_MASK	BIT(6)
+#define CFG_PLLCTL1_BWADJ_SHIFT	0
+#define CFG_PLLCTL1_BWADJ_MASK	0xf
+
+#define PLLM_RATIO_DIV1         (PLLDIV_ENABLE_MASK | 0x0)
+#define PLLM_RATIO_DIV2         (PLLDIV_ENABLE_MASK | 0x0)
+#define PLLM_RATIO_DIV3         (PLLDIV_ENABLE_MASK | 0x1)
+#define PLLM_RATIO_DIV4         (PLLDIV_ENABLE_MASK | 0x4)
+#define PLLM_RATIO_DIV5         (PLLDIV_ENABLE_MASK | 0x17)
+
+#define MISC_CTL1_ARM_PLL_EN	BIT(13)
 
 #endif  /* _CLOCK_DEFS_H_ */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 0cefb34..859a260 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -80,7 +80,6 @@ int board_eth_init(bd_t *bis)
 		return -1;
 	if (psc_enable_module(KS2_LPSC_CRYPTO))
 		return -1;
-	pass_pll_pa_clk_enable();
 
 	port_num = get_num_eth_ports();
 
-- 
2.1.4

[U-Boot] [PATCH 3/8] ARM: keystone2: Cleanup PLL init code

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:13PM +0530, Lokesh Vutla wrote:

> There are two types of PLL for all keystone platforms:
> Main PLL, Secondary PLL. Instead of duplicating the same definition
> for each secondary PLL, have a common function which does
> initialization for both PLLs. And also add proper register
> definitions.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 4/8] ARM: keystone2: Fix dev and arm speed detection

[Lokesh Vutla]

As per the Documentation for K2HK[1], K2L[2], K2E[3], the definition
of DEVSPEED register is same, only the supporting speeds are
different. Hence use the same speed definition for all platforms,
and read the DEVSPEED register to detect the supporting max speed.

[1] http://www.ti.com/lit/ds/symlink/66ak2h12.pdf
[2] http://www.ti.com/lit/ds/symlink/66ak2l06.pdf
[3] http://www.ti.com/lit/ds/symlink/am5k2e04.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock-k2e.c               | 16 ------
 arch/arm/mach-keystone/clock-k2hk.c              | 32 -----------
 arch/arm/mach-keystone/clock-k2l.c               | 32 -----------
 arch/arm/mach-keystone/clock.c                   | 71 ++++++++++++++----------
 arch/arm/mach-keystone/include/mach/clock-k2e.h  | 15 ++---
 arch/arm/mach-keystone/include/mach/clock-k2hk.h | 14 ++---
 arch/arm/mach-keystone/include/mach/clock-k2l.h  | 14 ++---
 arch/arm/mach-keystone/include/mach/clock.h      |  9 +++
 arch/arm/mach-keystone/include/mach/hardware.h   |  7 +++
 board/ti/ks2_evm/board_k2e.c                     |  1 -
 10 files changed, 73 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 31f6661..42092e1 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -17,22 +17,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 };
 
-int dev_speeds[] = {
-	SPD800,
-	SPD850,
-	SPD1000,
-	SPD1250,
-	SPD1350,
-	SPD1400,
-	SPD1500,
-	SPD1400,
-	SPD1350,
-	SPD1250,
-	SPD1000,
-	SPD850,
-	SPD800
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 1591960..96a9f72 100644
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
@@ -19,38 +19,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
-int dev_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-int arm_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD800,
-	SPD1400,
-	SPD1350,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 1c5e4d5..80c1f51 100644
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -18,38 +18,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 };
 
-int dev_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-int arm_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD800,
-	SPD1400,
-	SPD1350,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index d8311ca..cad9ff3 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -11,7 +11,19 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-#define MAX_SPEEDS		13
+/* DEV and ARM speed definitions as specified in DEVSPEED register */
+static int speeds[] = {
+	SPD1000,
+	SPD1200,
+	SPD1350,
+	SPD1400,
+	SPD1500,
+	SPD1400,
+	SPD1350,
+	SPD1200,
+	SPD1000,
+	SPD800,
+};
 
 static void wait_for_completion(const struct pll_init_data *data)
 {
@@ -179,43 +191,46 @@ void init_plls(int num_pll, struct pll_init_data *config)
 		init_pll(&config[i]);
 }
 
-static int get_max_speed(u32 val, int *speeds)
+static int get_max_speed(u32 val, u32 speed_supported)
 {
-	int j;
+	int speed;
 
-	if (!val)
-		return speeds[0];
-
-	for (j = 1; j < MAX_SPEEDS; j++) {
-		if (val == 1)
-			return speeds[j];
-		val >>= 1;
+	/* Left most setbit gives tess the speed */
+	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
+		if ((val & BIT(speed)) & speed_supported)
+			return speeds[speed];
 	}
 
+	/* If no bit is set, use SPD800 */
 	return SPD800;
 }
 
-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
-	return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
-		__raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
-static inline u32 read_efuse_bootrom(void)
+int get_max_arm_speed(void)
 {
-	return __raw_readl(KS2_EFUSE_BOOTROM);
-}
-#endif
+	int armspeed;
 
-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
-{
-	return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
+	if (cpu_revision() > 0)
+		armspeed = __raw_readl(KS2_REV1_DEVSPEED);
+	else
+		armspeed = __raw_readl(KS2_EFUSE_BOOTROM);
+
+	armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
+		    DEVSPEED_ARMSPEED_SHIFT;
+
+	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
 }
-#endif
 
-inline int get_max_dev_speed(void)
+int get_max_dev_speed(void)
 {
-	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+	int devspeed;
+
+	if (cpu_revision() > 0)
+		devspeed = __raw_readl(KS2_REV1_DEVSPEED);
+	else
+		devspeed = __raw_readl(KS2_EFUSE_BOOTROM);
+
+	devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
+		    DEVSPEED_DEVSPEED_SHIFT;
+
+	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
 }
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index 68e15ac..42be2ca 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -58,17 +58,6 @@ enum pll_type_e {
 	TETRIS_PLL,
 };
 
-enum {
-	SPD800,
-	SPD850,
-	SPD1000,
-	SPD1250,
-	SPD1350,
-	SPD1400,
-	SPD1500,
-	SPD_RSV
-};
-
 #define CORE_PLL_800	{CORE_PLL, 16, 1, 2}
 #define CORE_PLL_850	{CORE_PLL, 17, 1, 2}
 #define CORE_PLL_1000	{CORE_PLL, 20, 1, 2}
@@ -83,4 +72,8 @@ enum {
 #define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
 #define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
 
+/* k2e DEV supports 800, 1000, 1200, 1350, 1400, 1500 MHz */
+#define DEV_SUPPORTED_SPEEDS	0x3FF
+#define ARM_SUPPORTED_SPEEDS	0
+
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index f28d5f0..c41210c 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -64,15 +64,6 @@ enum pll_type_e {
 	DDR3B_PLL,
 };
 
-enum {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD_RSV
-};
-
 #define CORE_PLL_799    {CORE_PLL,	13,	1,	2}
 #define CORE_PLL_983    {CORE_PLL,	16,	1,	2}
 #define CORE_PLL_999	{CORE_PLL,	122,	15,	1}
@@ -100,4 +91,9 @@ enum {
 #define DDR3_PLL_800(x)	{DDR3##x##_PLL,	16,	1,	2}
 #define DDR3_PLL_333(x)	{DDR3##x##_PLL,	20,	1,	6}
 
+/* k2h DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS	0x383
+/* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
+#define ARM_SUPPORTED_SPEEDS	0x3EF
+
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4..c145a1e 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -59,15 +59,6 @@ enum pll_type_e {
 	DDR3_PLL,
 };
 
-enum {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD_RSV
-};
-
 #define CORE_PLL_799	{CORE_PLL, 13, 1, 2}
 #define CORE_PLL_983	{CORE_PLL, 16, 1, 2}
 #define CORE_PLL_1000	{CORE_PLL, 114, 7, 2}
@@ -92,4 +83,9 @@ enum {
 #define DDR3_PLL_800	{DDR3_PLL, 16, 1, 2}
 #define DDR3_PLL_333	{DDR3_PLL, 20, 1, 6}
 
+/* k2l DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS	0x383
+/* k2l ARM supportd 800, 1000, 1200, MHz */
+#define ARM_SUPPORTED_SPEEDS	0x383
+
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 7218230..2192c0d 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -32,6 +32,15 @@
 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
 #define CLOCK_INDEXES_LIST	CLK_LIST(GENERATE_INDX_STR)
 
+enum {
+	SPD800,
+	SPD1000,
+	SPD1200,
+	SPD1350,
+	SPD1400,
+	SPD1500,
+};
+
 enum clk_e {
 	CLK_LIST(GENERATE_ENUM)
 };
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 15c25b1..30022db 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -248,6 +248,13 @@ typedef volatile unsigned int   *dv_reg_p;
 #define CPU_66AK2Ex	0xb9a6
 #define CPU_66AK2Lx	0xb9a7
 
+/* DEVSPEED register */
+#define DEVSPEED_DEVSPEED_SHIFT	16
+#define DEVSPEED_DEVSPEED_MASK	(0xfff << 16)
+#define DEVSPEED_ARMSPEED_SHIFT	0
+#define DEVSPEED_ARMSPEED_MASK	0xfff
+#define DEVSPEED_NUMSPDS	12
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 43dfc48..6d98b2a 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -28,7 +28,6 @@ unsigned int external_clk[ext_clk_count] = {
 
 static struct pll_init_data core_pll_config[] = {
 	CORE_PLL_800,
-	CORE_PLL_850,
 	CORE_PLL_1000,
 	CORE_PLL_1250,
 	CORE_PLL_1350,
-- 
2.1.4

[U-Boot] [PATCH 4/8] ARM: keystone2: Fix dev and arm speed detection

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:14PM +0530, Lokesh Vutla wrote:

> As per the Documentation for K2HK[1], K2L[2], K2E[3], the definition
> of DEVSPEED register is same, only the supporting speeds are
> different. Hence use the same speed definition for all platforms,
> and read the DEVSPEED register to detect the supporting max speed.
> 
> [1] http://www.ti.com/lit/ds/symlink/66ak2h12.pdf
> [2] http://www.ti.com/lit/ds/symlink/66ak2l06.pdf
> [3] http://www.ti.com/lit/ds/symlink/am5k2e04.pdf
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 5/8] ARM: keystone2: Use common structure for PLLs

[Lokesh Vutla]

Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock-k2e.c                  |  6 ------
 arch/arm/mach-keystone/clock-k2hk.c                 |  8 --------
 arch/arm/mach-keystone/clock-k2l.c                  |  7 -------
 arch/arm/mach-keystone/clock.c                      |  8 ++++++++
 arch/arm/mach-keystone/include/mach/clock-k2e.h     |  8 --------
 arch/arm/mach-keystone/include/mach/clock-k2hk.h    |  9 ---------
 arch/arm/mach-keystone/include/mach/clock-k2l.h     |  8 --------
 arch/arm/mach-keystone/include/mach/clock.h         | 13 ++++++++++++-
 arch/arm/mach-keystone/include/mach/hardware-k2hk.h |  4 ----
 arch/arm/mach-keystone/include/mach/hardware.h      |  2 ++
 10 files changed, 22 insertions(+), 51 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 42092e1..b23d2a5 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -11,12 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 96a9f72..2e36891 100644
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
@@ -11,14 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
-	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 80c1f51..0bd0fd6 100644
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -11,13 +11,6 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clock_defs.h>
 
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
-	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
 /**
  * pll_freq_get - get pll frequency
  * Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index cad9ff3..f60a0b8 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -25,6 +25,14 @@ static int speeds[] = {
 	SPD800,
 };
 
+const struct keystone_pll_regs keystone_pll_regs[] = {
+	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+};
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
 	int i;
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index 42be2ca..3bde6da 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -50,14 +50,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6	sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	DDR3_PLL,
-	TETRIS_PLL,
-};
-
 #define CORE_PLL_800	{CORE_PLL, 16, 1, 2}
 #define CORE_PLL_850	{CORE_PLL, 17, 1, 2}
 #define CORE_PLL_1000	{CORE_PLL, 20, 1, 2}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index c41210c..366bf0e 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -55,15 +55,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6 sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	TETRIS_PLL,
-	DDR3A_PLL,
-	DDR3B_PLL,
-};
-
 #define CORE_PLL_799    {CORE_PLL,	13,	1,	2}
 #define CORE_PLL_983    {CORE_PLL,	16,	1,	2}
 #define CORE_PLL_999	{CORE_PLL,	122,	15,	1}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index c145a1e..e3f005a 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -51,14 +51,6 @@ extern unsigned int external_clk[ext_clk_count];
 
 #define KS2_CLK1_6	sys_clk0_6_clk
 
-/* PLL identifiers */
-enum pll_type_e {
-	CORE_PLL,
-	PASS_PLL,
-	TETRIS_PLL,
-	DDR3_PLL,
-};
-
 #define CORE_PLL_799	{CORE_PLL, 13, 1, 2}
 #define CORE_PLL_983	{CORE_PLL, 16, 1, 2}
 #define CORE_PLL_1000	{CORE_PLL, 114, 7, 2}
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 2192c0d..dc3c56a 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -24,7 +24,8 @@
 #include <asm/arch/clock-k2l.h>
 #endif
 
-#define MAIN_PLL CORE_PLL
+#define CORE_PLL MAIN_PLL
+#define DDR3_PLL DDR3A_PLL
 
 #include <asm/types.h>
 
@@ -41,6 +42,16 @@ enum {
 	SPD1500,
 };
 
+/* PLL identifiers */
+enum {
+	MAIN_PLL,
+	TETRIS_PLL,
+	PASS_PLL,
+	DDR3A_PLL,
+	DDR3B_PLL,
+	MAX_PLL_COUNT,
+};
+
 enum clk_e {
 	CLK_LIST(GENERATE_ENUM)
 };
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
index 195c0d3..8c771dc 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2hk.h
@@ -15,10 +15,6 @@
 /* PA SS Registers */
 #define KS2_PASS_BASE			0x02000000
 
-/* PLL control registers */
-#define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_MOD			0
 #define KS2_LPSC_DUMMY1			1
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 30022db..6d4015c 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -165,6 +165,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
 #define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
 #define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
 
-- 
2.1.4

[U-Boot] [PATCH 5/8] ARM: keystone2: Use common structure for PLLs

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:15PM +0530, Lokesh Vutla wrote:

> Register Base addresses are same for PLLs in all
> keystone platforms. If a PLL is not available, the corresponding
> register addresses are marked as reserved.
> Hence use a common definition.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 6/8] ARM: keystone2: Cleanup init_pll definition

[Lokesh Vutla]

This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock.c              | 12 ++++++---
 arch/arm/mach-keystone/include/mach/clock.h |  3 ++-
 board/ti/ks2_evm/board_k2e.c                | 33 +++++++++++++++--------
 board/ti/ks2_evm/board_k2hk.c               | 41 ++++++++++++++++++-----------
 board/ti/ks2_evm/board_k2l.c                | 41 ++++++++++++++++++-----------
 5 files changed, 84 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index f60a0b8..824a6ce 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -191,12 +191,16 @@ void init_pll(const struct pll_init_data *data)
 		configure_secondary_pll(data);
 }
 
-void init_plls(int num_pll, struct pll_init_data *config)
+void init_plls(void)
 {
-	int i;
+	struct pll_init_data *data;
+	int pll;
 
-	for (i = 0; i < num_pll; i++)
-		init_pll(&config[i]);
+	for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
+		data = get_pll_init_data(pll);
+		if (data)
+			init_pll(data);
+	}
 }
 
 static int get_max_speed(u32 val, u32 speed_supported)
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index dc3c56a..ea7d8bc 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -73,8 +73,9 @@ extern const struct keystone_pll_regs keystone_pll_regs[];
 extern int dev_speeds[];
 extern int arm_speeds[];
 
-void init_plls(int num_pll, struct pll_init_data *config);
+void init_plls(void);
 void init_pll(const struct pll_init_data *data);
+struct pll_init_data *get_pll_init_data(int pll);
 unsigned long clk_get_rate(unsigned int clk);
 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 6d98b2a..82792ef 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -38,6 +38,26 @@ static struct pll_init_data core_pll_config[] = {
 static struct pll_init_data pa_pll_config =
 	PASS_PLL_1000;
 
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed();
+		data = &core_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 struct eth_priv_t eth_priv_cfg[] = {
 	{
@@ -107,24 +127,15 @@ int get_num_eth_ports(void)
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
-	int speed;
-
-	speed = get_max_dev_speed();
-	init_pll(&core_pll_config[speed]);
-
-	init_pll(&pa_pll_config);
+	init_plls();
 
 	return 0;
 }
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
-	CORE_PLL_800,
-};
-
 void spl_init_keystone_plls(void)
 {
-	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+	init_plls();
 }
 #endif
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index ed181f4..cec6c02 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -46,6 +46,30 @@ static struct pll_init_data tetris_pll_config[] = {
 static struct pll_init_data pa_pll_config =
 	PASS_PLL_983;
 
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed();
+		data = &core_pll_config[speed];
+		break;
+	case TETRIS_PLL:
+		speed = get_max_arm_speed();
+		data = &tetris_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 struct eth_priv_t eth_priv_cfg[] = {
 	{
@@ -87,28 +111,15 @@ int get_num_eth_ports(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	int speed;
-
-	speed = get_max_dev_speed();
-	init_pll(&core_pll_config[speed]);
-
-	init_pll(&pa_pll_config);
-
-	speed = get_max_arm_speed();
-	init_pll(&tetris_pll_config[speed]);
+	init_plls();
 
 	return 0;
 }
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
-	CORE_PLL_799,
-	TETRIS_PLL_500,
-};
-
 void spl_init_keystone_plls(void)
 {
-	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+	init_plls();
 }
 #endif
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 729a193..1b4d086 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -42,6 +42,30 @@ static struct pll_init_data tetris_pll_config[] = {
 static struct pll_init_data pa_pll_config =
 	PASS_PLL_983;
 
+struct pll_init_data *get_pll_init_data(int pll)
+{
+	int speed;
+	struct pll_init_data *data;
+
+	switch (pll) {
+	case MAIN_PLL:
+		speed = get_max_dev_speed();
+		data = &core_pll_config[speed];
+		break;
+	case TETRIS_PLL:
+		speed = get_max_arm_speed();
+		data = &tetris_pll_config[speed];
+		break;
+	case PASS_PLL:
+		data = &pa_pll_config;
+		break;
+	default:
+		data = NULL;
+	}
+
+	return data;
+}
+
 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 struct eth_priv_t eth_priv_cfg[] = {
 	{
@@ -83,28 +107,15 @@ int get_num_eth_ports(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	int speed;
-
-	speed = get_max_dev_speed();
-	init_pll(&core_pll_config[speed]);
-
-	init_pll(&pa_pll_config);
-
-	speed = get_max_arm_speed();
-	init_pll(&tetris_pll_config[speed]);
+	init_plls();
 
 	return 0;
 }
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
-	CORE_PLL_799,
-	TETRIS_PLL_491,
-};
-
 void spl_init_keystone_plls(void)
 {
-	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+	init_plls();
 }
 #endif
-- 
2.1.4

[U-Boot] [PATCH 6/8] ARM: keystone2: Cleanup init_pll definition

[Vitaly Andrianov]

On 07/22/2015 11:39 AM, Lokesh Vutla wrote:
> This is just a cosmetic change that makes
> the calling of pll init code looks much cleaner.
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> ---
>   arch/arm/mach-keystone/clock.c              | 12 ++++++---
>   arch/arm/mach-keystone/include/mach/clock.h |  3 ++-
>   board/ti/ks2_evm/board_k2e.c                | 33 +++++++++++++++--------
>   board/ti/ks2_evm/board_k2hk.c               | 41 ++++++++++++++++++-----------
>   board/ti/ks2_evm/board_k2l.c                | 41 ++++++++++++++++++-----------
>   5 files changed, 84 insertions(+), 46 deletions(-)
>
> diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
> index f60a0b8..824a6ce 100644
> --- a/arch/arm/mach-keystone/clock.c
> +++ b/arch/arm/mach-keystone/clock.c
> @@ -191,12 +191,16 @@ void init_pll(const struct pll_init_data *data)
>   		configure_secondary_pll(data);
>   }
>
> -void init_plls(int num_pll, struct pll_init_data *config)
> +void init_plls(void)
>   {
> -	int i;
> +	struct pll_init_data *data;
> +	int pll;
>
> -	for (i = 0; i < num_pll; i++)
> -		init_pll(&config[i]);
> +	for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
> +		data = get_pll_init_data(pll);
> +		if (data)
> +			init_pll(data);
> +	}
>   }
>
Does the MAX_PLL_COUNT represent all PLLs on board?
If that is true, I think the patch is incorrect.
If you look at the history of the PLL configuration code you will find
that we had this cod in the past and changed it.

The currently working code doesn't configure all PLLs an advance.
For example DDR3a PLLs is configured later, after getting information
about required DDR3 speed. Also the current version of code doesn't 
configure DDR3B at all. And I don't see any reason why do we need to 
change it.




>   static int get_max_speed(u32 val, u32 speed_supported)
> diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
> index dc3c56a..ea7d8bc 100644
> --- a/arch/arm/mach-keystone/include/mach/clock.h
> +++ b/arch/arm/mach-keystone/include/mach/clock.h
> @@ -73,8 +73,9 @@ extern const struct keystone_pll_regs keystone_pll_regs[];
>   extern int dev_speeds[];
>   extern int arm_speeds[];
>
> -void init_plls(int num_pll, struct pll_init_data *config);
> +void init_plls(void);
>   void init_pll(const struct pll_init_data *data);
> +struct pll_init_data *get_pll_init_data(int pll);
>   unsigned long clk_get_rate(unsigned int clk);
>   unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
>   int clk_set_rate(unsigned int clk, unsigned long hz);
> diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
> index 6d98b2a..82792ef 100644
> --- a/board/ti/ks2_evm/board_k2e.c
> +++ b/board/ti/ks2_evm/board_k2e.c
> @@ -38,6 +38,26 @@ static struct pll_init_data core_pll_config[] = {
>   static struct pll_init_data pa_pll_config =
>   	PASS_PLL_1000;
>
> +struct pll_init_data *get_pll_init_data(int pll)
> +{
> +	int speed;
> +	struct pll_init_data *data;
> +
> +	switch (pll) {
> +	case MAIN_PLL:
> +		speed = get_max_dev_speed();
> +		data = &core_pll_config[speed];
> +		break;
> +	case PASS_PLL:
> +		data = &pa_pll_config;
> +		break;
> +	default:
> +		data = NULL;
> +	}
> +
> +	return data;
> +}
> +
>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>   struct eth_priv_t eth_priv_cfg[] = {
>   	{
> @@ -107,24 +127,15 @@ int get_num_eth_ports(void)
>   #if defined(CONFIG_BOARD_EARLY_INIT_F)
>   int board_early_init_f(void)
>   {
> -	int speed;
> -
> -	speed = get_max_dev_speed();
> -	init_pll(&core_pll_config[speed]);
> -
> -	init_pll(&pa_pll_config);
> +	init_plls();
>
>   	return 0;
>   }
>   #endif
>
>   #ifdef CONFIG_SPL_BUILD
> -static struct pll_init_data spl_pll_config[] = {
> -	CORE_PLL_800,
> -};
> -
>   void spl_init_keystone_plls(void)
>   {
> -	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
> +	init_plls();
>   }
>   #endif
> diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
> index ed181f4..cec6c02 100644
> --- a/board/ti/ks2_evm/board_k2hk.c
> +++ b/board/ti/ks2_evm/board_k2hk.c
> @@ -46,6 +46,30 @@ static struct pll_init_data tetris_pll_config[] = {
>   static struct pll_init_data pa_pll_config =
>   	PASS_PLL_983;
>
> +struct pll_init_data *get_pll_init_data(int pll)
> +{
> +	int speed;
> +	struct pll_init_data *data;
> +
> +	switch (pll) {
> +	case MAIN_PLL:
> +		speed = get_max_dev_speed();
> +		data = &core_pll_config[speed];
> +		break;
> +	case TETRIS_PLL:
> +		speed = get_max_arm_speed();
> +		data = &tetris_pll_config[speed];
> +		break;
> +	case PASS_PLL:
> +		data = &pa_pll_config;
> +		break;
> +	default:
> +		data = NULL;
> +	}
> +
> +	return data;
> +}
> +
>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>   struct eth_priv_t eth_priv_cfg[] = {
>   	{
> @@ -87,28 +111,15 @@ int get_num_eth_ports(void)
>   #ifdef CONFIG_BOARD_EARLY_INIT_F
>   int board_early_init_f(void)
>   {
> -	int speed;
> -
> -	speed = get_max_dev_speed();
> -	init_pll(&core_pll_config[speed]);
> -
> -	init_pll(&pa_pll_config);
> -
> -	speed = get_max_arm_speed();
> -	init_pll(&tetris_pll_config[speed]);
> +	init_plls();
>
>   	return 0;
>   }
>   #endif
>
>   #ifdef CONFIG_SPL_BUILD
> -static struct pll_init_data spl_pll_config[] = {
> -	CORE_PLL_799,
> -	TETRIS_PLL_500,
> -};
> -
>   void spl_init_keystone_plls(void)
>   {
> -	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
> +	init_plls();
>   }
>   #endif
> diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
> index 729a193..1b4d086 100644
> --- a/board/ti/ks2_evm/board_k2l.c
> +++ b/board/ti/ks2_evm/board_k2l.c
> @@ -42,6 +42,30 @@ static struct pll_init_data tetris_pll_config[] = {
>   static struct pll_init_data pa_pll_config =
>   	PASS_PLL_983;
>
> +struct pll_init_data *get_pll_init_data(int pll)
> +{
> +	int speed;
> +	struct pll_init_data *data;
> +
> +	switch (pll) {
> +	case MAIN_PLL:
> +		speed = get_max_dev_speed();
> +		data = &core_pll_config[speed];
> +		break;
> +	case TETRIS_PLL:
> +		speed = get_max_arm_speed();
> +		data = &tetris_pll_config[speed];
> +		break;
> +	case PASS_PLL:
> +		data = &pa_pll_config;
> +		break;
> +	default:
> +		data = NULL;
> +	}
> +
> +	return data;
> +}
> +
>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>   struct eth_priv_t eth_priv_cfg[] = {
>   	{
> @@ -83,28 +107,15 @@ int get_num_eth_ports(void)
>   #ifdef CONFIG_BOARD_EARLY_INIT_F
>   int board_early_init_f(void)
>   {
> -	int speed;
> -
> -	speed = get_max_dev_speed();
> -	init_pll(&core_pll_config[speed]);
> -
> -	init_pll(&pa_pll_config);
> -
> -	speed = get_max_arm_speed();
> -	init_pll(&tetris_pll_config[speed]);
> +	init_plls();
>
>   	return 0;
>   }
>   #endif
>
>   #ifdef CONFIG_SPL_BUILD
> -static struct pll_init_data spl_pll_config[] = {
> -	CORE_PLL_799,
> -	TETRIS_PLL_491,
> -};
> -
>   void spl_init_keystone_plls(void)
>   {
> -	init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
> +	init_plls();
>   }
>   #endif
>

[U-Boot] [PATCH 6/8] ARM: keystone2: Cleanup init_pll definition

[Lokesh Vutla]

Hi Vitaly,
On Thursday 23 July 2015 11:31 PM, Vitaly Andrianov wrote:
>
>
> On 07/22/2015 11:39 AM, Lokesh Vutla wrote:
>> This is just a cosmetic change that makes
>> the calling of pll init code looks much cleaner.
>>
>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>> ---
>>   arch/arm/mach-keystone/clock.c              | 12 ++++++---
>>   arch/arm/mach-keystone/include/mach/clock.h |  3 ++-
>>   board/ti/ks2_evm/board_k2e.c                | 33
>> +++++++++++++++--------
>>   board/ti/ks2_evm/board_k2hk.c               | 41
>> ++++++++++++++++++-----------
>>   board/ti/ks2_evm/board_k2l.c                | 41
>> ++++++++++++++++++-----------
>>   5 files changed, 84 insertions(+), 46 deletions(-)
>>
>> diff --git a/arch/arm/mach-keystone/clock.c
>> b/arch/arm/mach-keystone/clock.c
>> index f60a0b8..824a6ce 100644
>> --- a/arch/arm/mach-keystone/clock.c
>> +++ b/arch/arm/mach-keystone/clock.c
>> @@ -191,12 +191,16 @@ void init_pll(const struct pll_init_data *data)
>>           configure_secondary_pll(data);
>>   }
>>
>> -void init_plls(int num_pll, struct pll_init_data *config)
>> +void init_plls(void)
>>   {
>> -    int i;
>> +    struct pll_init_data *data;
>> +    int pll;
>>
>> -    for (i = 0; i < num_pll; i++)
>> -        init_pll(&config[i]);
>> +    for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
>> +        data = get_pll_init_data(pll);
>> +        if (data)
>> +            init_pll(data);
>> +    }
>>   }
>>
> Does the MAX_PLL_COUNT represent all PLLs on board?
It includes all except DDR. I haven't touched DDR yet.
> If that is true, I think the patch is incorrect.
> If you look at the history of the PLL configuration code you will find
> that we had this cod in the past and changed it.
May I know why DDR pll cannot be initialized along with other PLLs?
>
> The currently working code doesn't configure all PLLs an advance.
> For example DDR3a PLLs is configured later, after getting information
> about required DDR3 speed. Also the current version of code doesn't
> configure DDR3B at all. And I don't see any reason why do we need to
> change it.
So, get_pll_init_data() is defined in every board file and passes the 
correct
pll data. If pll is not available, it passes NULL so pll is not initialized.

Instead of calling init_pll for each pll separately, I made a single 
function
which takes care of all this stuff.

Thanks and regards,
Lokesh
>
>
>
>
>>   static int get_max_speed(u32 val, u32 speed_supported)
>> diff --git a/arch/arm/mach-keystone/include/mach/clock.h
>> b/arch/arm/mach-keystone/include/mach/clock.h
>> index dc3c56a..ea7d8bc 100644
>> --- a/arch/arm/mach-keystone/include/mach/clock.h
>> +++ b/arch/arm/mach-keystone/include/mach/clock.h
>> @@ -73,8 +73,9 @@ extern const struct keystone_pll_regs
>> keystone_pll_regs[];
>>   extern int dev_speeds[];
>>   extern int arm_speeds[];
>>
>> -void init_plls(int num_pll, struct pll_init_data *config);
>> +void init_plls(void);
>>   void init_pll(const struct pll_init_data *data);
>> +struct pll_init_data *get_pll_init_data(int pll);
>>   unsigned long clk_get_rate(unsigned int clk);
>>   unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
>>   int clk_set_rate(unsigned int clk, unsigned long hz);
>> diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
>> index 6d98b2a..82792ef 100644
>> --- a/board/ti/ks2_evm/board_k2e.c
>> +++ b/board/ti/ks2_evm/board_k2e.c
>> @@ -38,6 +38,26 @@ static struct pll_init_data core_pll_config[] = {
>>   static struct pll_init_data pa_pll_config =
>>       PASS_PLL_1000;
>>
>> +struct pll_init_data *get_pll_init_data(int pll)
>> +{
>> +    int speed;
>> +    struct pll_init_data *data;
>> +
>> +    switch (pll) {
>> +    case MAIN_PLL:
>> +        speed = get_max_dev_speed();
>> +        data = &core_pll_config[speed];
>> +        break;
>> +    case PASS_PLL:
>> +        data = &pa_pll_config;
>> +        break;
>> +    default:
>> +        data = NULL;
>> +    }
>> +
>> +    return data;
>> +}
>> +
>>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>>   struct eth_priv_t eth_priv_cfg[] = {
>>       {
>> @@ -107,24 +127,15 @@ int get_num_eth_ports(void)
>>   #if defined(CONFIG_BOARD_EARLY_INIT_F)
>>   int board_early_init_f(void)
>>   {
>> -    int speed;
>> -
>> -    speed = get_max_dev_speed();
>> -    init_pll(&core_pll_config[speed]);
>> -
>> -    init_pll(&pa_pll_config);
>> +    init_plls();
>>
>>       return 0;
>>   }
>>   #endif
>>
>>   #ifdef CONFIG_SPL_BUILD
>> -static struct pll_init_data spl_pll_config[] = {
>> -    CORE_PLL_800,
>> -};
>> -
>>   void spl_init_keystone_plls(void)
>>   {
>> -    init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
>> +    init_plls();
>>   }
>>   #endif
>> diff --git a/board/ti/ks2_evm/board_k2hk.c
>> b/board/ti/ks2_evm/board_k2hk.c
>> index ed181f4..cec6c02 100644
>> --- a/board/ti/ks2_evm/board_k2hk.c
>> +++ b/board/ti/ks2_evm/board_k2hk.c
>> @@ -46,6 +46,30 @@ static struct pll_init_data tetris_pll_config[] = {
>>   static struct pll_init_data pa_pll_config =
>>       PASS_PLL_983;
>>
>> +struct pll_init_data *get_pll_init_data(int pll)
>> +{
>> +    int speed;
>> +    struct pll_init_data *data;
>> +
>> +    switch (pll) {
>> +    case MAIN_PLL:
>> +        speed = get_max_dev_speed();
>> +        data = &core_pll_config[speed];
>> +        break;
>> +    case TETRIS_PLL:
>> +        speed = get_max_arm_speed();
>> +        data = &tetris_pll_config[speed];
>> +        break;
>> +    case PASS_PLL:
>> +        data = &pa_pll_config;
>> +        break;
>> +    default:
>> +        data = NULL;
>> +    }
>> +
>> +    return data;
>> +}
>> +
>>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>>   struct eth_priv_t eth_priv_cfg[] = {
>>       {
>> @@ -87,28 +111,15 @@ int get_num_eth_ports(void)
>>   #ifdef CONFIG_BOARD_EARLY_INIT_F
>>   int board_early_init_f(void)
>>   {
>> -    int speed;
>> -
>> -    speed = get_max_dev_speed();
>> -    init_pll(&core_pll_config[speed]);
>> -
>> -    init_pll(&pa_pll_config);
>> -
>> -    speed = get_max_arm_speed();
>> -    init_pll(&tetris_pll_config[speed]);
>> +    init_plls();
>>
>>       return 0;
>>   }
>>   #endif
>>
>>   #ifdef CONFIG_SPL_BUILD
>> -static struct pll_init_data spl_pll_config[] = {
>> -    CORE_PLL_799,
>> -    TETRIS_PLL_500,
>> -};
>> -
>>   void spl_init_keystone_plls(void)
>>   {
>> -    init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
>> +    init_plls();
>>   }
>>   #endif
>> diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
>> index 729a193..1b4d086 100644
>> --- a/board/ti/ks2_evm/board_k2l.c
>> +++ b/board/ti/ks2_evm/board_k2l.c
>> @@ -42,6 +42,30 @@ static struct pll_init_data tetris_pll_config[] = {
>>   static struct pll_init_data pa_pll_config =
>>       PASS_PLL_983;
>>
>> +struct pll_init_data *get_pll_init_data(int pll)
>> +{
>> +    int speed;
>> +    struct pll_init_data *data;
>> +
>> +    switch (pll) {
>> +    case MAIN_PLL:
>> +        speed = get_max_dev_speed();
>> +        data = &core_pll_config[speed];
>> +        break;
>> +    case TETRIS_PLL:
>> +        speed = get_max_arm_speed();
>> +        data = &tetris_pll_config[speed];
>> +        break;
>> +    case PASS_PLL:
>> +        data = &pa_pll_config;
>> +        break;
>> +    default:
>> +        data = NULL;
>> +    }
>> +
>> +    return data;
>> +}
>> +
>>   #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
>>   struct eth_priv_t eth_priv_cfg[] = {
>>       {
>> @@ -83,28 +107,15 @@ int get_num_eth_ports(void)
>>   #ifdef CONFIG_BOARD_EARLY_INIT_F
>>   int board_early_init_f(void)
>>   {
>> -    int speed;
>> -
>> -    speed = get_max_dev_speed();
>> -    init_pll(&core_pll_config[speed]);
>> -
>> -    init_pll(&pa_pll_config);
>> -
>> -    speed = get_max_arm_speed();
>> -    init_pll(&tetris_pll_config[speed]);
>> +    init_plls();
>>
>>       return 0;
>>   }
>>   #endif
>>
>>   #ifdef CONFIG_SPL_BUILD
>> -static struct pll_init_data spl_pll_config[] = {
>> -    CORE_PLL_799,
>> -    TETRIS_PLL_491,
>> -};
>> -
>>   void spl_init_keystone_plls(void)
>>   {
>> -    init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
>> +    init_plls();
>>   }
>>   #endif
>>

[U-Boot] [PATCH 6/8] ARM: keystone2: Cleanup init_pll definition

[Vitaly Andrianov]

Lokesh,

On 07/24/2015 12:20 AM, Lokesh Vutla wrote:
> Hi Vitaly,
> On Thursday 23 July 2015 11:31 PM, Vitaly Andrianov wrote:
>>
>>
>> On 07/22/2015 11:39 AM, Lokesh Vutla wrote:
>>> This is just a cosmetic change that makes
>>> the calling of pll init code looks much cleaner.
>>>
>>> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
>>> ---
>>>   arch/arm/mach-keystone/clock.c              | 12 ++++++---
>>>   arch/arm/mach-keystone/include/mach/clock.h |  3 ++-
>>>   board/ti/ks2_evm/board_k2e.c                | 33
>>> +++++++++++++++--------
>>>   board/ti/ks2_evm/board_k2hk.c               | 41
>>> ++++++++++++++++++-----------
>>>   board/ti/ks2_evm/board_k2l.c                | 41
>>> ++++++++++++++++++-----------
>>>   5 files changed, 84 insertions(+), 46 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-keystone/clock.c
>>> b/arch/arm/mach-keystone/clock.c
>>> index f60a0b8..824a6ce 100644
>>> --- a/arch/arm/mach-keystone/clock.c
>>> +++ b/arch/arm/mach-keystone/clock.c
>>> @@ -191,12 +191,16 @@ void init_pll(const struct pll_init_data *data)
>>>           configure_secondary_pll(data);
>>>   }
>>>
>>> -void init_plls(int num_pll, struct pll_init_data *config)
>>> +void init_plls(void)
>>>   {
>>> -    int i;
>>> +    struct pll_init_data *data;
>>> +    int pll;
>>>
>>> -    for (i = 0; i < num_pll; i++)
>>> -        init_pll(&config[i]);
>>> +    for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
>>> +        data = get_pll_init_data(pll);
>>> +        if (data)
>>> +            init_pll(data);
>>> +    }
>>>   }
>>>
>> Does the MAX_PLL_COUNT represent all PLLs on board?
> It includes all except DDR. I haven't touched DDR yet.
I see.

>> If that is true, I think the patch is incorrect.
>> If you look at the history of the PLL configuration code you will find
>> that we had this cod in the past and changed it.
> May I know why DDR pll cannot be initialized along with other PLLs?
The DDR PLL is to be configured later after reading SPD data and finding 
out required DDR3 speed.

>>
>> The currently working code doesn't configure all PLLs an advance.
>> For example DDR3a PLLs is configured later, after getting information
>> about required DDR3 speed. Also the current version of code doesn't
>> configure DDR3B at all. And I don't see any reason why do we need to
>> change it.
> So, get_pll_init_data() is defined in every board file and passes the
> correct
> pll data. If pll is not available, it passes NULL so pll is not
> initialized.
>
> Instead of calling init_pll for each pll separately, I made a single
> function
> which takes care of all this stuff.
>
> Thanks and regards,
> Lokesh
>>
>>

[snip]

Reviewed-by: Vitaly Andrianov <vitalya@ti.com>

[U-Boot] [PATCH 6/8] ARM: keystone2: Cleanup init_pll definition

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:16PM +0530, Lokesh Vutla wrote:

> This is just a cosmetic change that makes
> the calling of pll init code looks much cleaner.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 7/8] ARM: keystone2: Remove unsed external clocks

[Lokesh Vutla]

Remove unused external clocks and make a common definition
for all keystone platforms.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/clock-k2e.c               |  2 +-
 arch/arm/mach-keystone/clock-k2l.c               |  2 +-
 arch/arm/mach-keystone/include/mach/clock-k2e.h  | 15 ---------------
 arch/arm/mach-keystone/include/mach/clock-k2hk.h | 18 ------------------
 arch/arm/mach-keystone/include/mach/clock-k2l.h  | 15 ---------------
 arch/arm/mach-keystone/include/mach/clock.h      | 11 +++++++++++
 board/ti/ks2_evm/board_k2e.c                     |  7 +------
 board/ti/ks2_evm/board_k2hk.c                    |  6 ------
 board/ti/ks2_evm/board_k2l.c                     |  5 +----
 9 files changed, 15 insertions(+), 66 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index b23d2a5..7d163a4 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -43,7 +43,7 @@ static unsigned long pll_freq_get(int pll)
 			reg = KS2_PASSPLLCTL0;
 			break;
 		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
+			ret = external_clk[ddr3a_clk];
 			reg = KS2_DDR3APLLCTL0;
 			break;
 		default:
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 0bd0fd6..0004059 100644
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
 			reg = KS2_ARMPLLCTL0;
 			break;
 		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
+			ret = external_clk[ddr3a_clk];
 			reg = KS2_DDR3APLLCTL0;
 			break;
 		default:
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index 3bde6da..e2467e7 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -10,21 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2E_H
 #define __ASM_ARCH_CLOCK_K2E_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	ddr3_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_clk,
-	xgmii_clk,
-	usb_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index 366bf0e..775a9cb 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -10,24 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3a_clk,
-	ddr3b_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_srio_clk,
-	xgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index e3f005a..485746d 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,21 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3_clk,
-	pcie_clk,
-	sgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index ea7d8bc..2509d5d 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -52,6 +52,16 @@ enum {
 	MAX_PLL_COUNT,
 };
 
+enum ext_clk_e {
+	sys_clk,
+	alt_core_clk,
+	pa_clk,
+	tetris_clk,
+	ddr3a_clk,
+	ddr3b_clk,
+	ext_clk_count /* number of external clocks */
+};
+
 enum clk_e {
 	CLK_LIST(GENERATE_ENUM)
 };
@@ -69,6 +79,7 @@ struct pll_init_data {
 	int pll_od;		/* PLL output divider */
 };
 
+extern unsigned int external_clk[ext_clk_count];
 extern const struct keystone_pll_regs keystone_pll_regs[];
 extern int dev_speeds[];
 extern int arm_speeds[];
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 82792ef..93e29c7 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -18,12 +18,7 @@ unsigned int external_clk[ext_clk_count] = {
 	[sys_clk]	= 100000000,
 	[alt_core_clk]	= 100000000,
 	[pa_clk]	= 100000000,
-	[ddr3_clk]	= 100000000,
-	[mcm_clk]	= 312500000,
-	[pcie_clk]	= 100000000,
-	[sgmii_clk]	= 156250000,
-	[xgmii_clk]	= 156250000,
-	[usb_clk]	= 100000000,
+	[ddr3a_clk]	= 100000000,
 };
 
 static struct pll_init_data core_pll_config[] = {
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index cec6c02..c3d485e 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -21,12 +21,6 @@ unsigned int external_clk[ext_clk_count] = {
 	[tetris_clk]	=	125000000,
 	[ddr3a_clk]	=	100000000,
 	[ddr3b_clk]	=	100000000,
-	[mcm_clk]	=	312500000,
-	[pcie_clk]	=	100000000,
-	[sgmii_srio_clk] =	156250000,
-	[xgmii_clk]	=	156250000,
-	[usb_clk]	=	100000000,
-	[rp1_clk]	=	123456789
 };
 
 static struct pll_init_data core_pll_config[] = {
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 1b4d086..9199d0b 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -19,10 +19,7 @@ unsigned int external_clk[ext_clk_count] = {
 	[alt_core_clk]	= 100000000,
 	[pa_clk]	= 122880000,
 	[tetris_clk]	= 122880000,
-	[ddr3_clk]	= 100000000,
-	[pcie_clk]	= 100000000,
-	[sgmii_clk]	= 156250000,
-	[usb_clk]	= 100000000,
+	[ddr3a_clk]	= 100000000,
 };
 
 static struct pll_init_data core_pll_config[] = {
-- 
2.1.4

[U-Boot] [PATCH 7/8] ARM: keystone2: Remove unsed external clocks

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:17PM +0530, Lokesh Vutla wrote:

> Remove unused external clocks and make a common definition
> for all keystone platforms.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 8/8] ARM: keystone2: Use common definition for clk_get_rate

[Lokesh Vutla]

Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/mach-keystone/Makefile                  |   3 -
 arch/arm/mach-keystone/clock-k2e.c               |  95 ----------------
 arch/arm/mach-keystone/clock-k2hk.c              | 105 -----------------
 arch/arm/mach-keystone/clock-k2l.c               |  99 ----------------
 arch/arm/mach-keystone/clock.c                   | 139 +++++++++++++++++++++++
 arch/arm/mach-keystone/cmd_clock.c               |   7 +-
 arch/arm/mach-keystone/include/mach/clock-k2e.h  |  21 ----
 arch/arm/mach-keystone/include/mach/clock-k2hk.h |  23 ----
 arch/arm/mach-keystone/include/mach/clock-k2l.h  |  22 ----
 arch/arm/mach-keystone/include/mach/clock.h      |  23 ++++
 arch/arm/mach-keystone/include/mach/clock_defs.h |  32 ------
 11 files changed, 167 insertions(+), 402 deletions(-)
 delete mode 100644 arch/arm/mach-keystone/clock-k2e.c
 delete mode 100644 arch/arm/mach-keystone/clock-k2hk.c
 delete mode 100644 arch/arm/mach-keystone/clock-k2l.c

diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ed030db..ffd9ead 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -8,9 +8,6 @@
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o
-obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
-obj-$(CONFIG_SOC_K2E) += clock-k2e.o
-obj-$(CONFIG_SOC_K2L) += clock-k2l.o
 obj-y	+= cmd_clock.o
 obj-y	+= cmd_mon.o
 obj-y	+= msmc.o
diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
deleted file mode 100644
index 7d163a4..0000000
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
deleted file mode 100644
index 2e36891..0000000
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
deleted file mode 100644
index 0004059..0000000
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 824a6ce..54f30d7 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -246,3 +246,142 @@ int get_max_dev_speed(void)
 
 	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
 }
+
+/**
+ * pll_freq_get - get pll frequency
+ * @pll:	pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, output_div = 2;
+	unsigned long ret;
+	u32 tmp, reg;
+
+	if (pll == MAIN_PLL) {
+		ret = external_clk[sys_clk];
+		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
+			/* PLL mode */
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
+			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
+			mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
+				CFG_PLLCTL0_PLLM_SHIFT |
+				(pllctl_reg_read(pll, mult) &
+				 PLLM_MULT_LO_MASK)) + 1;
+			output_div = ((pllctl_reg_read(pll, secctl) &
+				       SECCTL_OP_DIV_MASK) >>
+				       SECCTL_OP_DIV_SHIFT) + 1;
+
+			ret = ret / prediv / output_div * mult;
+		}
+	} else {
+		switch (pll) {
+		case PASS_PLL:
+			ret = external_clk[pa_clk];
+			reg = KS2_PASSPLLCTL0;
+			break;
+		case TETRIS_PLL:
+			ret = external_clk[tetris_clk];
+			reg = KS2_ARMPLLCTL0;
+			break;
+		case DDR3A_PLL:
+			ret = external_clk[ddr3a_clk];
+			reg = KS2_DDR3APLLCTL0;
+			break;
+		case DDR3B_PLL:
+			ret = external_clk[ddr3b_clk];
+			reg = KS2_DDR3BPLLCTL0;
+			break;
+		default:
+			return 0;
+		}
+
+		tmp = __raw_readl(reg);
+
+		if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
+			/* Bypass disabled */
+			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
+			mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
+				CFG_PLLCTL0_PLLM_SHIFT) + 1;
+			output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
+				      CFG_PLLCTL0_CLKOD_SHIFT) + 1;
+			ret = ((ret / prediv) * mult) / output_div;
+		}
+	}
+
+	return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	unsigned long freq = 0;
+
+	switch (clk) {
+	case core_pll_clk:
+		freq = pll_freq_get(CORE_PLL);
+		break;
+	case pass_pll_clk:
+		freq = pll_freq_get(PASS_PLL);
+		break;
+	case tetris_pll_clk:
+		if (!cpu_is_k2e())
+			freq = pll_freq_get(TETRIS_PLL);
+		break;
+	case ddr3a_pll_clk:
+		freq = pll_freq_get(DDR3A_PLL);
+		break;
+	case ddr3b_pll_clk:
+		if (cpu_is_k2hk())
+			freq = pll_freq_get(DDR3B_PLL);
+		break;
+	case sys_clk0_1_clk:
+	case sys_clk0_clk:
+		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
+		break;
+	case sys_clk1_clk:
+	return pll_freq_get(CORE_PLL) / pll0div_read(2);
+		break;
+	case sys_clk2_clk:
+		freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
+		break;
+	case sys_clk3_clk:
+		freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
+		break;
+	case sys_clk0_2_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 2;
+		break;
+	case sys_clk0_3_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 3;
+		break;
+	case sys_clk0_4_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 4;
+		break;
+	case sys_clk0_6_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 6;
+		break;
+	case sys_clk0_8_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 8;
+		break;
+	case sys_clk0_12_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 12;
+		break;
+	case sys_clk0_24_clk:
+		freq = clk_get_rate(sys_clk0_clk) / 24;
+		break;
+	case sys_clk1_3_clk:
+		freq = clk_get_rate(sys_clk1_clk) / 3;
+		break;
+	case sys_clk1_4_clk:
+		freq = clk_get_rate(sys_clk1_clk) / 4;
+		break;
+	case sys_clk1_6_clk:
+		freq = clk_get_rate(sys_clk1_clk) / 6;
+		break;
+	case sys_clk1_12_clk:
+		freq = clk_get_rate(sys_clk1_clk) / 12;
+		break;
+	default:
+		break;
+	}
+
+	return freq;
+}
diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c
index af1b701..3d5cf3f 100644
--- a/arch/arm/mach-keystone/cmd_clock.c
+++ b/arch/arm/mach-keystone/cmd_clock.c
@@ -67,7 +67,7 @@ U_BOOT_CMD(
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned int clk;
-	unsigned int freq;
+	unsigned long freq;
 
 	if (argc != 2)
 		goto getclk_cmd_usage;
@@ -75,7 +75,10 @@ int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	clk = simple_strtoul(argv[1], NULL, 10);
 
 	freq = clk_get_rate(clk);
-	printf("clock index [%d] - frequency %u\n", clk, freq);
+	if (freq)
+		printf("clock index [%d] - frequency %lu\n", clk, freq);
+	else
+		printf("clock index [%d] Not available\n", clk);
 	return 0;
 
 getclk_cmd_usage:
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index e2467e7..f0c6f7a 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -10,27 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2E_H
 #define __ASM_ARCH_CLOCK_K2E_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, ddr3_pll_clk)\
-	CLK(3, sys_clk0_clk)\
-	CLK(4, sys_clk0_1_clk)\
-	CLK(5, sys_clk0_2_clk)\
-	CLK(6, sys_clk0_3_clk)\
-	CLK(7, sys_clk0_4_clk)\
-	CLK(8, sys_clk0_6_clk)\
-	CLK(9, sys_clk0_8_clk)\
-	CLK(10, sys_clk0_12_clk)\
-	CLK(11, sys_clk0_24_clk)\
-	CLK(12, sys_clk1_clk)\
-	CLK(13, sys_clk1_3_clk)\
-	CLK(14, sys_clk1_4_clk)\
-	CLK(15, sys_clk1_6_clk)\
-	CLK(16, sys_clk1_12_clk)\
-	CLK(17, sys_clk2_clk)\
-	CLK(18, sys_clk3_clk)
-
 #define PLLSET_CMD_LIST	"<pa|ddr3>"
 
 #define KS2_CLK1_6	sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index 775a9cb..b8f3e76 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -10,29 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3a_pll_clk)\
-	CLK(4, ddr3b_pll_clk)\
-	CLK(5, sys_clk0_clk)\
-	CLK(6, sys_clk0_1_clk)\
-	CLK(7, sys_clk0_2_clk)\
-	CLK(8, sys_clk0_3_clk)\
-	CLK(9, sys_clk0_4_clk)\
-	CLK(10, sys_clk0_6_clk)\
-	CLK(11, sys_clk0_8_clk)\
-	CLK(12, sys_clk0_12_clk)\
-	CLK(13, sys_clk0_24_clk)\
-	CLK(14, sys_clk1_clk)\
-	CLK(15, sys_clk1_3_clk)\
-	CLK(16, sys_clk1_4_clk)\
-	CLK(17, sys_clk1_6_clk)\
-	CLK(18, sys_clk1_12_clk)\
-	CLK(19, sys_clk2_clk)\
-	CLK(20, sys_clk3_clk)
-
 #define PLLSET_CMD_LIST		"<pa|arm|ddr3a|ddr3b>"
 
 #define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index 485746d..8772a7d 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -10,28 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-#define CLK_LIST(CLK)\
-	CLK(0, core_pll_clk)\
-	CLK(1, pass_pll_clk)\
-	CLK(2, tetris_pll_clk)\
-	CLK(3, ddr3_pll_clk)\
-	CLK(4, sys_clk0_clk)\
-	CLK(5, sys_clk0_1_clk)\
-	CLK(6, sys_clk0_2_clk)\
-	CLK(7, sys_clk0_3_clk)\
-	CLK(8, sys_clk0_4_clk)\
-	CLK(9, sys_clk0_6_clk)\
-	CLK(10, sys_clk0_8_clk)\
-	CLK(11, sys_clk0_12_clk)\
-	CLK(12, sys_clk0_24_clk)\
-	CLK(13, sys_clk1_clk)\
-	CLK(14, sys_clk1_3_clk)\
-	CLK(15, sys_clk1_4_clk)\
-	CLK(16, sys_clk1_6_clk)\
-	CLK(17, sys_clk1_12_clk)\
-	CLK(18, sys_clk2_clk)\
-	CLK(19, sys_clk3_clk)\
-
 #define PLLSET_CMD_LIST	"<pa|arm|ddr3>"
 
 #define KS2_CLK1_6	sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 2509d5d..6e0cf22 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -27,6 +27,29 @@
 #define CORE_PLL MAIN_PLL
 #define DDR3_PLL DDR3A_PLL
 
+#define CLK_LIST(CLK)\
+	CLK(0, core_pll_clk)\
+	CLK(1, pass_pll_clk)\
+	CLK(2, tetris_pll_clk)\
+	CLK(3, ddr3a_pll_clk)\
+	CLK(4, ddr3b_pll_clk)\
+	CLK(5, sys_clk0_clk)\
+	CLK(6, sys_clk0_1_clk)\
+	CLK(7, sys_clk0_2_clk)\
+	CLK(8, sys_clk0_3_clk)\
+	CLK(9, sys_clk0_4_clk)\
+	CLK(10, sys_clk0_6_clk)\
+	CLK(11, sys_clk0_8_clk)\
+	CLK(12, sys_clk0_12_clk)\
+	CLK(13, sys_clk0_24_clk)\
+	CLK(14, sys_clk1_clk)\
+	CLK(15, sys_clk1_3_clk)\
+	CLK(16, sys_clk1_4_clk)\
+	CLK(17, sys_clk1_6_clk)\
+	CLK(18, sys_clk1_12_clk)\
+	CLK(19, sys_clk2_clk)\
+	CLK(20, sys_clk3_clk)
+
 #include <asm/types.h>
 
 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index ff12689..f2ca423 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -69,38 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
 
 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
 
-#define PLLCTL_BYPASS           BIT(23)
-#define PLL_PLLRST              BIT(14)
-#define PLLCTL_PAPLL            BIT(13)
-#define PLLCTL_CLKMODE          BIT(8)
-#define PLLCTL_PLLSELB          BIT(7)
-#define PLLCTL_ENSAT            BIT(6)
-#define PLLCTL_PLLENSRC         BIT(5)
-#define PLLCTL_PLLDIS           BIT(4)
-#define PLLCTL_PLLRST           BIT(3)
-#define PLLCTL_PLLPWRDN         BIT(1)
-#define PLLCTL_PLLEN            BIT(0)
-#define PLLSTAT_GO              BIT(0)
-
-#define MAIN_ENSAT_OFFSET       6
-
-#define PLLDIV_ENABLE           BIT(15)
-
-#define PLL_DIV_MASK            0x3f
-#define PLL_MULT_MASK           0x1fff
-#define PLL_MULT_SHIFT          6
-#define PLLM_MULT_HI_MASK       0x7f
-#define PLLM_MULT_HI_SHIFT      12
-#define PLLM_MULT_HI_SMASK      (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
-#define PLLM_MULT_LO_MASK       0x3f
-#define PLL_CLKOD_MASK          0xf
-#define PLL_CLKOD_SHIFT         19
-#define PLL_CLKOD_SMASK         (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
-#define PLL_BWADJ_LO_MASK       0xff
-#define PLL_BWADJ_LO_SHIFT      24
-#define PLL_BWADJ_LO_SMASK      (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
-#define PLL_BWADJ_HI_MASK       0xf
-
 /* PLLCTL Bits */
 #define PLLCTL_PLLENSRC_SHIF	5
 #define PLLCTL_PLLENSRC_MASK	BIT(5)
-- 
2.1.4

[U-Boot] [PATCH 8/8] ARM: keystone2: Use common definition for clk_get_rate

[Tom Rini]

On Wed, Jul 22, 2015 at 09:09:18PM +0530, Lokesh Vutla wrote:

> Since all the clocks are defined common, and has the same logic to get
> the frequencies, use a common definition for for clk_get_rate().
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH 0/8] ARM: keystone2: Clocls and PLLs cleanup

[Lokesh Vutla]

Hi,
On Wednesday 22 July 2015 09:09 PM, Lokesh Vutla wrote:
> This seires does a several bunch of cleanups for clock and PLL
> related definitions. This helps a lot in adding data for
> new Keystone2 SoCs. And also adds support for CPU detection.
Sorry about the typo in $subject. Will update it after the comments
on this series.

Thanks and regards,
Lokesh
>
> This is based on Nishanth's config cleanup series:
> https://www.mail-archive.com/u-boot%40lists.denx.de/msg177822.html
>
> Tested on K2HK-evm: http://pastebin.ubuntu.com/11920541/
>
> Lokesh Vutla (8):
>    ARM: keystone2: Cleanup SoC detection
>    ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFO
>    ARM: keystone2: Cleanup PLL init code
>    ARM: keystone2: Fix dev and arm speed detection
>    ARM: keystone2: Use common address for PLL
>    ARM: keystone2: Cleanup pll calling
>    ARM: keystone2: Remove unsed externalk clocks
>    ARM: keystone2: Use common definition for clk_get_rate
>
>   arch/arm/mach-keystone/Makefile                    |   3 -
>   arch/arm/mach-keystone/clock-k2e.c                 | 117 -----
>   arch/arm/mach-keystone/clock-k2hk.c                | 145 ------
>   arch/arm/mach-keystone/clock-k2l.c                 | 138 ------
>   arch/arm/mach-keystone/clock.c                     | 527 +++++++++++++--------
>   arch/arm/mach-keystone/cmd_clock.c                 |   7 +-
>   arch/arm/mach-keystone/include/mach/clock-k2e.h    |  58 +--
>   arch/arm/mach-keystone/include/mach/clock-k2hk.h   |  64 +--
>   arch/arm/mach-keystone/include/mach/clock-k2l.h    |  59 +--
>   arch/arm/mach-keystone/include/mach/clock.h        |  60 ++-
>   arch/arm/mach-keystone/include/mach/clock_defs.h   | 107 +++--
>   .../arm/mach-keystone/include/mach/hardware-k2hk.h |   4 -
>   arch/arm/mach-keystone/include/mach/hardware.h     |  51 +-
>   arch/arm/mach-keystone/init.c                      |  24 +
>   board/ti/ks2_evm/board.c                           |   1 -
>   board/ti/ks2_evm/board_k2e.c                       |  41 +-
>   board/ti/ks2_evm/board_k2hk.c                      |  47 +-
>   board/ti/ks2_evm/board_k2l.c                       |  46 +-
>   include/configs/ti_armv7_keystone2.h               |   1 +
>   19 files changed, 603 insertions(+), 897 deletions(-)
>   delete mode 100644 arch/arm/mach-keystone/clock-k2e.c
>   delete mode 100644 arch/arm/mach-keystone/clock-k2hk.c
>   delete mode 100644 arch/arm/mach-keystone/clock-k2l.c
>