From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mugunthan V N <mugunthanvnm@ti.com>
Date: Thu, 23 Jul 2015 19:44:38 +0530
Subject: [U-Boot] [PATCH 1/1] driver: net: keystone_net: fix phy mode
 configuration
In-Reply-To: <55B0EE3A.4040101@linaro.org>
References: <1437642108-20155-1-git-send-email-mugunthanvnm@ti.com>
 <55B0CD18.2090202@linaro.org> <55B0E165.8020805@ti.com>
 <55B0EE3A.4040101@linaro.org>
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On Thursday 23 July 2015 07:08 PM, Ivan Khoronzhuk wrote:
> 
> 
> On 23.07.15 15:43, Mugunthan V N wrote:
>> On Thursday 23 July 2015 04:46 PM, Ivan Khoronzhuk wrote:
>>> Hi, Mugunthan
>>>
>>> You are right, phy mode is a board property.
>>> But just for clarifying, does Ethernet SS, which contains SGMII
>>> on board, support another i/f mode except SGMII? Can it work
>>> w/o SerDes?
>>
>> There is a upcoming SoC (K2E) using the same IP with RGMII phy
>> connected. So the IP is capable of supporting multiple phy modes.
>>
>> Regards
>> Mugunthan V N
>>
> 
> Then I would ask you to add it in commit message.
> Also, if it can work in RGMII mode, could you please check if a
> following errata doesn't affect you configuration.
> This is only for Marvell phys, and if it's your case, it be good,
> probably, to extend it`s impact on RGMII mode also.
> 
> net: phy: marvell: add errata w/a for 88E151* chips
> 35fa0dda0ccee8075b1ef8922e930d5dcdea9f5e

It uses Micrel phy.

Regards
Mugunthan V N