[U-Boot] [PATCH 4/8] ARM: keystone2: Fix dev and arm speed detection

Lokesh Vutla
2015-07-22T15:39:14Z

As per the Documentation for K2HK[1], K2L[2], K2E[3], the definition
of DEVSPEED register is same, only the supporting speeds are
different. Hence use the same speed definition for all platforms,
and read the DEVSPEED register to detect the supporting max speed.

[1] http://www.ti.com/lit/ds/symlink/66ak2h12.pdf
[2] http://www.ti.com/lit/ds/symlink/66ak2l06.pdf
[3] http://www.ti.com/lit/ds/symlink/am5k2e04.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm/mach-keystone/clock-k2e.c | 16 ------
arch/arm/mach-keystone/clock-k2hk.c | 32 -----------
arch/arm/mach-keystone/clock-k2l.c | 32 -----------
arch/arm/mach-keystone/clock.c | 71 ++++++++++++++----------
arch/arm/mach-keystone/include/mach/clock-k2e.h | 15 ++---
arch/arm/mach-keystone/include/mach/clock-k2hk.h | 14 ++---
arch/arm/mach-keystone/include/mach/clock-k2l.h | 14 ++---
arch/arm/mach-keystone/include/mach/clock.h | 9 +++
arch/arm/mach-keystone/include/mach/hardware.h | 7 +++
board/ti/ks2_evm/board_k2e.c | 1 -
10 files changed, 73 insertions(+), 138 deletions(-)

diff --git a/arch/arm/mach-keystone/clock-k2e.c b/arch/arm/mach-keystone/clock-k2e.c
index 31f6661..42092e1 100644
--- a/arch/arm/mach-keystone/clock-k2e.c
+++ b/arch/arm/mach-keystone/clock-k2e.c
@@ -17,22 +17,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};

-int dev_speeds[] = {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD1400,
- SPD1350,
- SPD1250,
- SPD1000,
- SPD850,
- SPD800
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2hk.c b/arch/arm/mach-keystone/clock-k2hk.c
index 1591960..96a9f72 100644
--- a/arch/arm/mach-keystone/clock-k2hk.c
+++ b/arch/arm/mach-keystone/clock-k2hk.c
@@ -19,38 +19,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};

-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock-k2l.c b/arch/arm/mach-keystone/clock-k2l.c
index 1c5e4d5..80c1f51 100644
--- a/arch/arm/mach-keystone/clock-k2l.c
+++ b/arch/arm/mach-keystone/clock-k2l.c
@@ -18,38 +18,6 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};

-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index d8311ca..cad9ff3 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -11,7 +11,19 @@
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>

-#define MAX_SPEEDS 13
+/* DEV and ARM speed definitions as specified in DEVSPEED register */
+static int speeds[] = {
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+ SPD1400,
+ SPD1350,
+ SPD1200,
+ SPD1000,
+ SPD800,
+};

static void wait_for_completion(const struct pll_init_data *data)
{
@@ -179,43 +191,46 @@ void init_plls(int num_pll, struct pll_init_data *config)
init_pll(&config[i]);
}

-static int get_max_speed(u32 val, int *speeds)
+static int get_max_speed(u32 val, u32 speed_supported)
{
- int j;
+ int speed;

- if (!val)
- return speeds[0];
-
- for (j = 1; j < MAX_SPEEDS; j++) {
- if (val == 1)
- return speeds[j];
- val >>= 1;
+ /* Left most setbit gives tess the speed */
+ for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
+ if ((val & BIT(speed)) & speed_supported)
+ return speeds[speed];
}

+ /* If no bit is set, use SPD800 */
return SPD800;
}

-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
- return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
- __raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
-static inline u32 read_efuse_bootrom(void)
+int get_max_arm_speed(void)
{
- return __raw_readl(KS2_EFUSE_BOOTROM);
-}
-#endif
+ int armspeed;

-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
-{
- return get_max_speed(read_efuse_bootrom() & 0xffff, arm_speeds);
+ if (cpu_revision() > 0)
+ armspeed = __raw_readl(KS2_REV1_DEVSPEED);
+ else
+ armspeed = __raw_readl(KS2_EFUSE_BOOTROM);
+
+ armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
+ DEVSPEED_ARMSPEED_SHIFT;
+
+ return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
}
-#endif

-inline int get_max_dev_speed(void)
+int get_max_dev_speed(void)
{
- return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, dev_speeds);
+ int devspeed;
+
+ if (cpu_revision() > 0)
+ devspeed = __raw_readl(KS2_REV1_DEVSPEED);
+ else
+ devspeed = __raw_readl(KS2_EFUSE_BOOTROM);
+
+ devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
+ DEVSPEED_DEVSPEED_SHIFT;
+
+ return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
}
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2e.h b/arch/arm/mach-keystone/include/mach/clock-k2e.h
index 68e15ac..42be2ca 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2e.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2e.h
@@ -58,17 +58,6 @@ enum pll_type_e {
TETRIS_PLL,
};

-enum {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD_RSV
-};
-
#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
@@ -83,4 +72,8 @@ enum {
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}

+/* k2e DEV supports 800, 1000, 1200, 1350, 1400, 1500 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x3FF
+#define ARM_SUPPORTED_SPEEDS 0
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2hk.h b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
index f28d5f0..c41210c 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2hk.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2hk.h
@@ -64,15 +64,6 @@ enum pll_type_e {
DDR3B_PLL,
};

-enum {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD_RSV
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_999 {CORE_PLL, 122, 15, 1}
@@ -100,4 +91,9 @@ enum {
#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}

+/* k2h DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x383
+/* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
+#define ARM_SUPPORTED_SPEEDS 0x3EF
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4..c145a1e 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -59,15 +59,6 @@ enum pll_type_e {
DDR3_PLL,
};

-enum {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD_RSV
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
@@ -92,4 +83,9 @@ enum {
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}

+/* k2l DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x383
+/* k2l ARM supportd 800, 1000, 1200, MHz */
+#define ARM_SUPPORTED_SPEEDS 0x383
+
#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index 7218230..2192c0d 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -32,6 +32,15 @@
#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)

+enum {
+ SPD800,
+ SPD1000,
+ SPD1200,
+ SPD1350,
+ SPD1400,
+ SPD1500,
+};
+
enum clk_e {
CLK_LIST(GENERATE_ENUM)
};
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 15c25b1..30022db 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -248,6 +248,13 @@ typedef volatile unsigned int *dv_reg_p;
#define CPU_66AK2Ex 0xb9a6
#define CPU_66AK2Lx 0xb9a7

+/* DEVSPEED register */
+#define DEVSPEED_DEVSPEED_SHIFT 16
+#define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
+#define DEVSPEED_ARMSPEED_SHIFT 0
+#define DEVSPEED_ARMSPEED_MASK 0xfff
+#define DEVSPEED_NUMSPDS 12
+
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 43dfc48..6d98b2a 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -28,7 +28,6 @@ unsigned int external_clk[ext_clk_count] = {

static struct pll_init_data core_pll_config[] = {
CORE_PLL_800,
- CORE_PLL_850,
CORE_PLL_1000,
CORE_PLL_1250,
CORE_PLL_1350,
--
2.1.4