* [U-Boot] [PATCH 02/19] ARM: zynq: DT: Add missing nodes to DTSI
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
@ 2015-07-22 15:37 ` Michal Simek
2015-07-22 15:37 ` [U-Boot] [PATCH 03/19] ARM: zynq: DT: Add a fixed regulator for CPU voltage Michal Simek
` (16 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:37 UTC (permalink / raw)
To: u-boot
Add ADC, CAN, GPIO, MC, DMA, DEVCFG, USB, Watchdog IPs to DTSI.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with the kernel.
---
arch/arm/dts/zynq-7000.dtsi | 100 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 6faac4044627..fc5dd4d4a38e 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -51,6 +51,48 @@
interrupt-parent = <&intc>;
ranges;
+ adc: adc at f8007100 {
+ compatible = "xlnx,zynq-xadc-1.00.a";
+ reg = <0xf8007100 0x20>;
+ interrupts = <0 7 4>;
+ interrupt-parent = <&intc>;
+ clocks = <&clkc 12>;
+ };
+
+ can0: can at e0008000 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clocks = <&clkc 19>, <&clkc 36>;
+ clock-names = "can_clk", "pclk";
+ reg = <0xe0008000 0x1000>;
+ interrupts = <0 28 4>;
+ interrupt-parent = <&intc>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ can1: can at e0009000 {
+ compatible = "xlnx,zynq-can-1.0";
+ status = "disabled";
+ clocks = <&clkc 20>, <&clkc 37>;
+ clock-names = "can_clk", "pclk";
+ reg = <0xe0009000 0x1000>;
+ interrupts = <0 51 4>;
+ interrupt-parent = <&intc>;
+ tx-fifo-depth = <0x40>;
+ rx-fifo-depth = <0x40>;
+ };
+
+ gpio0: gpio at e000a000 {
+ compatible = "xlnx,zynq-gpio-1.0";
+ #gpio-cells = <2>;
+ clocks = <&clkc 42>;
+ gpio-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <0 20 4>;
+ reg = <0xe000a000 0x1000>;
+ };
+
i2c0: i2c at e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
@@ -91,6 +133,11 @@
cache-level = <2>;
};
+ mc: memory-controller at f8006000 {
+ compatible = "xlnx,zynq-ddrc-a05";
+ reg = <0xf8006000 0x1000>;
+ };
+
uart0: serial at e0000000 {
compatible = "xlnx,xuartps";
status = "disabled";
@@ -199,6 +246,29 @@
};
};
+ dmac_s: dmac at f8003000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xf8003000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
+ "dma4", "dma5", "dma6", "dma7";
+ interrupts = <0 13 4>,
+ <0 14 4>, <0 15 4>,
+ <0 16 4>, <0 17 4>,
+ <0 40 4>, <0 41 4>,
+ <0 42 4>, <0 43 4>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <4>;
+ clocks = <&clkc 27>;
+ clock-names = "apb_pclk";
+ };
+
+ devcfg: devcfg at f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ };
+
global_timer: timer at f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
@@ -222,6 +292,7 @@
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
+
scutimer: timer at f8f00600 {
interrupt-parent = <&intc>;
interrupts = < 1 13 0x301 >;
@@ -229,5 +300,34 @@
reg = < 0xf8f00600 0x20 >;
clocks = <&clkc 4>;
} ;
+
+ usb0: usb at e0002000 {
+ compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+ status = "disabled";
+ clocks = <&clkc 28>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 21 4>;
+ reg = <0xe0002000 0x1000>;
+ phy_type = "ulpi";
+ };
+
+ usb1: usb at e0003000 {
+ compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+ status = "disabled";
+ clocks = <&clkc 29>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 44 4>;
+ reg = <0xe0003000 0x1000>;
+ phy_type = "ulpi";
+ };
+
+ watchdog0: watchdog at f8005000 {
+ clocks = <&clkc 45>;
+ compatible = "cdns,wdt-r1p2";
+ interrupt-parent = <&intc>;
+ interrupts = <0 9 1>;
+ reg = <0xf8005000 0x1000>;
+ timeout-sec = <10>;
+ };
};
};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 03/19] ARM: zynq: DT: Add a fixed regulator for CPU voltage
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
2015-07-22 15:37 ` [U-Boot] [PATCH 02/19] ARM: zynq: DT: Add missing nodes to DTSI Michal Simek
@ 2015-07-22 15:37 ` Michal Simek
2015-07-22 15:37 ` [U-Boot] [PATCH 04/19] ARM: zynq: DT: Migrate UART to Cadence binding Michal Simek
` (15 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:37 UTC (permalink / raw)
To: u-boot
To silence the warning
cpufreq_cpu0: failed to get cpu0 regulator: -19
from the cpufreq driver regarding a missing regulator,
add a fixed regulator to the DT.
Zynq does not support voltage scaling and the CPU rail should always be
supplied with 1 V, hence it is added in the SOC-level dtsi.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline kernel
---
arch/arm/dts/zynq-7000.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index fc5dd4d4a38e..326ab6766c56 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -21,6 +21,7 @@
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
+ cpu0-supply = <®ulator_vccpint>;
operating-points = <
/* kHz uV */
666667 1000000
@@ -44,6 +45,15 @@
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
+ regulator_vccpint: fixedregulator at 0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCPINT";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
amba {
compatible = "simple-bus";
#address-cells = <1>;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 04/19] ARM: zynq: DT: Migrate UART to Cadence binding
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
2015-07-22 15:37 ` [U-Boot] [PATCH 02/19] ARM: zynq: DT: Add missing nodes to DTSI Michal Simek
2015-07-22 15:37 ` [U-Boot] [PATCH 03/19] ARM: zynq: DT: Add a fixed regulator for CPU voltage Michal Simek
@ 2015-07-22 15:37 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 05/19] ARM: zynq: DT: Remove 222 MHz OPP Michal Simek
` (14 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:37 UTC (permalink / raw)
To: u-boot
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Mainline sync
---
arch/arm/dts/zynq-7000.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 326ab6766c56..a4bfc6211100 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -149,19 +149,19 @@
};
uart0: serial at e0000000 {
- compatible = "xlnx,xuartps";
+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
- clock-names = "ref_clk", "aper_clk";
+ clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};
uart1: serial at e0001000 {
- compatible = "xlnx,xuartps";
+ compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
- clock-names = "ref_clk", "aper_clk";
+ clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 05/19] ARM: zynq: DT: Remove 222 MHz OPP
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (2 preceding siblings ...)
2015-07-22 15:37 ` [U-Boot] [PATCH 04/19] ARM: zynq: DT: Migrate UART to Cadence binding Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 06/19] spi: Fix zynq SPI binding Michal Simek
` (13 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Due to dependencies between timer and CPU frequency, only changes by
powers of two are allowed. The clocksource driver prevents other
changes, but with cpufreq and its governors it can result in being
spammed with error messages constantly. Hence, remove the 222 MHz OPP.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
From mainline
---
arch/arm/dts/zynq-7000.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a4bfc6211100..7679cf242f91 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -26,7 +26,6 @@
/* kHz uV */
666667 1000000
333334 1000000
- 222223 1000000
>;
};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 06/19] spi: Fix zynq SPI binding
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (3 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 05/19] ARM: zynq: DT: Remove 222 MHz OPP Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-08-13 18:36 ` Jagan Teki
2015-07-22 15:38 ` [U-Boot] [PATCH 07/19] ARM: zynq: DT: Fix GEM register area size Michal Simek
` (12 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynq-7000.dtsi | 4 ++--
doc/device-tree-bindings/spi/spi-zynq.txt | 35 +++++++++++++++++--------------
drivers/spi/zynq_spi.c | 2 +-
3 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 7679cf242f91..d212b60ca6b2 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -166,7 +166,7 @@
};
spi0: spi at e0006000 {
- compatible = "xlnx,zynq-spi";
+ compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
@@ -179,7 +179,7 @@
};
spi1: spi at e0007000 {
- compatible = "xlnx,zynq-spi";
+ compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt
index f397a36d6801..cb2945789d05 100644
--- a/doc/device-tree-bindings/spi/spi-zynq.txt
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -1,29 +1,32 @@
-Zynq SPI controller Device Tree Bindings
-----------------------------------------
+Cadence SPI controller Device Tree Bindings
+-------------------------------------------
Required properties:
-- compatible : Should be "xlnx,spi-zynq".
+- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
- reg : Physical base address and size of SPI registers map.
-- status : Status will be disabled in dtsi and enabled in required dts.
-- interrupt-parent : Must be core interrupt controller.
- interrupts : Property with a value describing the interrupt
number.
-- clocks : Clock phandles (see clock bindings for details).
+- interrupt-parent : Must be core interrupt controller
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
+- clocks : Clock phandles (see clock bindings for details).
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
+Optional properties:
+- num-cs : Number of chip selects used.
+ If a decoder is used, this will be the number of
+ chip selects after the decoder.
+- is-decoded-cs : Flag to indicate whether decoder is used or not.
+
Example:
- spi at e0006000 {
- compatible = "xlnx,zynq-spi";
- reg = <0xe0006000 0x1000>;
- status = "disabled";
- interrupt-parent = <&intc>;
- interrupts = <0 26 4>;
- clocks = <&clkc 25>, <&clkc 34>;
+ spi at e0007000 {
+ compatible = "xlnx,zynq-spi-r1p6";
clock-names = "ref_clk", "pclk";
- spi-max-frequency = <166666700>;
- #address-cells = <1>;
- #size-cells = <0>;
+ clocks = <&clkc 26>, <&clkc 35>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 49 4>;
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ reg = <0xe0007000 0x1000>;
} ;
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index c5c3e1044fda..0208afc4a636 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -309,7 +309,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
};
static const struct udevice_id zynq_spi_ids[] = {
- { .compatible = "xlnx,zynq-spi" },
+ { .compatible = "xlnx,zynq-spi-r1p6" },
{ }
};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 06/19] spi: Fix zynq SPI binding
2015-07-22 15:38 ` [U-Boot] [PATCH 06/19] spi: Fix zynq SPI binding Michal Simek
@ 2015-08-13 18:36 ` Jagan Teki
0 siblings, 0 replies; 22+ messages in thread
From: Jagan Teki @ 2015-08-13 18:36 UTC (permalink / raw)
To: u-boot
On 22 July 2015 at 21:08, Michal Simek <michal.simek@xilinx.com> wrote:
> Zynq is using Cadence IP where binding is documented in the Linux kernel
> and there is no reason to use different binding.
> Synchronize it.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Updated patchwork, just take along with the series.
> ---
>
> arch/arm/dts/zynq-7000.dtsi | 4 ++--
> doc/device-tree-bindings/spi/spi-zynq.txt | 35 +++++++++++++++++--------------
> drivers/spi/zynq_spi.c | 2 +-
> 3 files changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index 7679cf242f91..d212b60ca6b2 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -166,7 +166,7 @@
> };
>
> spi0: spi at e0006000 {
> - compatible = "xlnx,zynq-spi";
> + compatible = "xlnx,zynq-spi-r1p6";
> reg = <0xe0006000 0x1000>;
> status = "disabled";
> interrupt-parent = <&intc>;
> @@ -179,7 +179,7 @@
> };
>
> spi1: spi at e0007000 {
> - compatible = "xlnx,zynq-spi";
> + compatible = "xlnx,zynq-spi-r1p6";
> reg = <0xe0007000 0x1000>;
> status = "disabled";
> interrupt-parent = <&intc>;
> diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt
> index f397a36d6801..cb2945789d05 100644
> --- a/doc/device-tree-bindings/spi/spi-zynq.txt
> +++ b/doc/device-tree-bindings/spi/spi-zynq.txt
> @@ -1,29 +1,32 @@
> -Zynq SPI controller Device Tree Bindings
> -----------------------------------------
> +Cadence SPI controller Device Tree Bindings
> +-------------------------------------------
>
> Required properties:
> -- compatible : Should be "xlnx,spi-zynq".
> +- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
> - reg : Physical base address and size of SPI registers map.
> -- status : Status will be disabled in dtsi and enabled in required dts.
> -- interrupt-parent : Must be core interrupt controller.
> - interrupts : Property with a value describing the interrupt
> number.
> -- clocks : Clock phandles (see clock bindings for details).
> +- interrupt-parent : Must be core interrupt controller
> - clock-names : List of input clock names - "ref_clk", "pclk"
> (See clock bindings for details).
> +- clocks : Clock phandles (see clock bindings for details).
> - spi-max-frequency : Maximum SPI clocking speed of device in Hz
>
> +Optional properties:
> +- num-cs : Number of chip selects used.
> + If a decoder is used, this will be the number of
> + chip selects after the decoder.
> +- is-decoded-cs : Flag to indicate whether decoder is used or not.
> +
> Example:
>
> - spi at e0006000 {
> - compatible = "xlnx,zynq-spi";
> - reg = <0xe0006000 0x1000>;
> - status = "disabled";
> - interrupt-parent = <&intc>;
> - interrupts = <0 26 4>;
> - clocks = <&clkc 25>, <&clkc 34>;
> + spi at e0007000 {
> + compatible = "xlnx,zynq-spi-r1p6";
> clock-names = "ref_clk", "pclk";
> - spi-max-frequency = <166666700>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> + clocks = <&clkc 26>, <&clkc 35>;
> + interrupt-parent = <&intc>;
> + interrupts = <0 49 4>;
> + num-cs = <4>;
> + is-decoded-cs = <0>;
> + reg = <0xe0007000 0x1000>;
> } ;
> diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
> index c5c3e1044fda..0208afc4a636 100644
> --- a/drivers/spi/zynq_spi.c
> +++ b/drivers/spi/zynq_spi.c
> @@ -309,7 +309,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
> };
>
> static const struct udevice_id zynq_spi_ids[] = {
> - { .compatible = "xlnx,zynq-spi" },
> + { .compatible = "xlnx,zynq-spi-r1p6" },
> { }
> };
>
> --
> 2.3.5
thanks!
--
Jagan | openedev.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 07/19] ARM: zynq: DT: Fix GEM register area size
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (4 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 06/19] spi: Fix zynq SPI binding Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 08/19] ARM: zynq: DT: Use the zynq binding with macb Michal Simek
` (11 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
The size of the GEM's register area is only 0x1000 bytes.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync from the kernel
---
arch/arm/dts/zynq-7000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index d212b60ca6b2..a8bbe4875465 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -193,7 +193,7 @@
gem0: ethernet at e000b000 {
compatible = "cdns,gem";
- reg = <0xe000b000 0x4000>;
+ reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -202,7 +202,7 @@
gem1: ethernet at e000c000 {
compatible = "cdns,gem";
- reg = <0xe000c000 0x4000>;
+ reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 08/19] ARM: zynq: DT: Use the zynq binding with macb
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (5 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 07/19] ARM: zynq: DT: Fix GEM register area size Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 09/19] ARM: zynq: DT: Clean up timer device tree nodes Michal Simek
` (10 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: S?ren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
From the kernel.
---
arch/arm/dts/zynq-7000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a8bbe4875465..383ddd674b08 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -192,7 +192,7 @@
};
gem0: ethernet at e000b000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
@@ -201,7 +201,7 @@
};
gem1: ethernet at e000c000 {
- compatible = "cdns,gem";
+ compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 09/19] ARM: zynq: DT: Clean up timer device tree nodes
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (6 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 08/19] ARM: zynq: DT: Use the zynq binding with macb Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 10/19] ARM: zynq: DT: Cleanup address-cells and size-cells Michal Simek
` (9 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Separate IRQ cells from each other for easier reading.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline kernel
---
arch/arm/dts/zynq-7000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 383ddd674b08..61256ee42393 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -288,7 +288,7 @@
ttc0: timer at f8001000 {
interrupt-parent = <&intc>;
- interrupts = < 0 10 4 0 11 4 0 12 4 >;
+ interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
@@ -296,7 +296,7 @@
ttc1: timer at f8002000 {
interrupt-parent = <&intc>;
- interrupts = < 0 37 4 0 38 4 0 39 4 >;
+ interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 10/19] ARM: zynq: DT: Cleanup address-cells and size-cells
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (7 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 09/19] ARM: zynq: DT: Clean up timer device tree nodes Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 11/19] ARM: zynq: DT: Add pinctrl node Michal Simek
` (8 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Remove unneeded address-cells form intc node because it is already setup
in parent node.
Add missing address-cells and size-cells to eth node to be shared for
every platform DTSes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline.
---
arch/arm/dts/zynq-7000.dtsi | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 61256ee42393..276aa75097fc 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -127,7 +127,6 @@
intc: interrupt-controller at f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
- #address-cells = <1>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
@@ -198,6 +197,8 @@
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
gem1: ethernet at e000c000 {
@@ -207,6 +208,8 @@
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
sdhci0: sdhci at e0100000 {
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 11/19] ARM: zynq: DT: Add pinctrl node
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (8 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 10/19] ARM: zynq: DT: Cleanup address-cells and size-cells Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 12/19] ARM: zynq: DT: Add reference to bus node Michal Simek
` (7 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Add pinctrl node to DTSI.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline.
---
arch/arm/dts/zynq-7000.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 276aa75097fc..109b7dc4dbe9 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -235,7 +235,7 @@
slcr: slcr at f8000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "xlnx,zynq-slcr", "syscon";
+ compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc at 100 {
@@ -256,6 +256,12 @@
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
+
+ pinctrl0: pinctrl at 700 {
+ compatible = "xlnx,pinctrl-zynq";
+ reg = <0x700 0x200>;
+ syscon = <&slcr>;
+ };
};
dmac_s: dmac at f8003000 {
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 12/19] ARM: zynq: DT: Add reference to bus node
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (9 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 11/19] ARM: zynq: DT: Add pinctrl node Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 13/19] ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel Michal Simek
` (6 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
For adding OCM memory in platform DTS is necessary to have reference to
amba bus.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline.
---
arch/arm/dts/zynq-7000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 109b7dc4dbe9..21b8c98ab2b3 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -53,7 +53,7 @@
regulator-always-on;
};
- amba {
+ amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 13/19] ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (10 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 12/19] ARM: zynq: DT: Add reference to bus node Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 14/19] ARM: zynq: DT: Update years in copyright Michal Simek
` (5 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Syncup with the latest DT from the Linux kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynq-zc702.dts | 351 +++++++++++++++++++++++++++++++++++++++++++-
arch/arm/dts/zynq-zc706.dts | 293 +++++++++++++++++++++++++++++++++++-
arch/arm/dts/zynq-zed.dts | 46 +++++-
arch/arm/dts/zynq-zybo.dts | 38 ++++-
4 files changed, 715 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 4fa0b00b318b..1c879846813e 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -1,7 +1,8 @@
/*
* Xilinx ZC702 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +10,359 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC702 Board";
+ model = "Zynq ZC702 Development Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
serial0 = &uart1;
};
memory {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
};
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ ds23 {
+ label = "ds23";
+ gpios = <&gpio0 10 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&amba {
+ ocm: sram at fffc0000 {
+ compatible = "mmio-sram";
+ reg = <0xfffc0000 0x10000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem0_default>;
+
+ ethernet_phy: ethernet-phy at 7 {
+ reg = <7>;
+ };
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+
+ i2cswitch at 74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ si570: clock-generator at 5d {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x5d>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ eeprom at 54 {
+ compatible = "at,24c08";
+ reg = <0x54>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio at 21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ rtc at 51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ hwmon at 52 {
+ compatible = "ti,ucd9248";
+ reg = <52>;
+ };
+ hwmon at 53 {
+ compatible = "ti,ucd9248";
+ reg = <53>;
+ };
+ hwmon at 54 {
+ compatible = "ti,ucd9248";
+ reg = <54>;
+ };
+ };
+ };
+};
+
+&pinctrl0 {
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_9_grp";
+ };
+
+ conf {
+ groups = "can0_9_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO46";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO47";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem0_default: gem0-default {
+ mux {
+ function = "ethernet0";
+ groups = "ethernet0_0_grp";
+ };
+
+ conf {
+ groups = "ethernet0_0_grp";
+ slew-rate = <0>;
+ io-standard = <4>;
+ };
+
+ conf-rx {
+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio0";
+ groups = "mdio0_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio0_default: gpio0-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
+ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
+ "gpio0_13_grp", "gpio0_14_grp";
+ };
+
+ conf {
+ groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
+ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
+ "gpio0_13_grp", "gpio0_14_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-pull-up {
+ pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO7", "MIO8";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_10_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_10_grp";
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_2_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_2_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "gpio0_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "gpio0_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ mux-wp {
+ groups = "gpio0_15_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "gpio0_15_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO49";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO48";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts
index 2a80195757db..cf7bce4468de 100644
--- a/arch/arm/dts/zynq-zc706.dts
+++ b/arch/arm/dts/zynq-zc706.dts
@@ -1,7 +1,8 @@
/*
* Xilinx ZC706 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +10,301 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC706 Board";
+ model = "Zynq ZC706 Development Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
serial0 = &uart1;
};
memory {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
};
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem0_default>;
+
+ ethernet_phy: ethernet-phy at 7 {
+ reg = <7>;
+ };
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio0_default>;
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+
+ i2cswitch at 74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ si570: clock-generator at 5d {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x5d>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ eeprom at 54 {
+ compatible = "at,24c08";
+ reg = <0x54>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio at 21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ rtc at 51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ ucd90120 at 65 {
+ compatible = "ti,ucd90120";
+ reg = <0x65>;
+ };
+ };
+ };
+};
+
+&pinctrl0 {
+ pinctrl_gem0_default: gem0-default {
+ mux {
+ function = "ethernet0";
+ groups = "ethernet0_0_grp";
+ };
+
+ conf {
+ groups = "ethernet0_0_grp";
+ slew-rate = <0>;
+ io-standard = <4>;
+ };
+
+ conf-rx {
+ pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
+ low-power-enable;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio0";
+ groups = "mdio0_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_gpio0_default: gpio0-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
+ };
+
+ conf {
+ groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-pull-up {
+ pins = "MIO46", "MIO47";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO7";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_10_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_10_grp";
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_2_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_2_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "gpio0_14_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "gpio0_14_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ mux-wp {
+ groups = "gpio0_15_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "gpio0_15_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO49";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO48";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO29", "MIO31", "MIO36";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
+ "MIO35", "MIO37", "MIO38", "MIO39";
+ bias-disable;
+ };
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 70cc8a6c0d75..5762576fea2d 100644
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,7 +1,8 @@
/*
* Xilinx ZED board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +10,54 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZED Board";
+ model = "Zynq Zed Development Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
aliases {
+ ethernet0 = &gem0;
serial0 = &uart1;
};
memory {
device_type = "memory";
- reg = <0 0x20000000>;
+ reg = <0x0 0x20000000>;
};
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&clkc {
+ ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy at 0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
};
diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
index 20e03867773a..10f78155244d 100644
--- a/arch/arm/dts/zynq-zybo.dts
+++ b/arch/arm/dts/zynq-zybo.dts
@@ -1,7 +1,8 @@
/*
* Digilent ZYBO board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +10,44 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZYBO Board";
- compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
+ model = "Zynq ZYBO Development Board";
+ compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
aliases {
+ ethernet0 = &gem0;
serial0 = &uart1;
};
memory {
device_type = "memory";
- reg = <0 0x20000000>;
+ reg = <0x0 0x20000000>;
};
+
+ chosen {
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+&clkc {
+ ps-clk-frequency = <50000000>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy at 0 {
+ reg = <0>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 14/19] ARM: zynq: DT: Update years in copyright
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (11 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 13/19] ARM: zynq: DT: Sync zc702/zc706/zed/zybo DT with kernel Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency Michal Simek
` (4 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Trivial.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
DTSI are coming from the same source that's why I have synced years
according the Linux kernel.
---
arch/arm/dts/zynq-7000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 21b8c98ab2b3..a1de993b9812 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -2,7 +2,7 @@
* Xilinx Zynq 7000 DTSI
* Describes the hardware common to all Zynq 7000-based boards.
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2011 - 2015 Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (12 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 14/19] ARM: zynq: DT: Update years in copyright Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:51 ` Sören Brinkmann
2015-07-22 15:38 ` [U-Boot] [PATCH 16/19] ARM: zynq: DT: Add missing interrupt for L2 pl310 Michal Simek
` (3 subsequent siblings)
17 siblings, 1 reply; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
ps-clk-frequency is platform specific setting and shouldn't be the part
of DTSI.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Sync with mainline.
---
arch/arm/dts/zynq-7000.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a1de993b9812..095c0f67e167 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -241,7 +241,6 @@
clkc: clkc at 100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- ps-clk-frequency = <33333333>;
fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency
2015-07-22 15:38 ` [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency Michal Simek
@ 2015-07-22 15:51 ` Sören Brinkmann
2015-07-24 12:47 ` Michal Simek
0 siblings, 1 reply; 22+ messages in thread
From: Sören Brinkmann @ 2015-07-22 15:51 UTC (permalink / raw)
To: u-boot
On Wed, 2015-07-22 at 05:38PM +0200, Michal Simek wrote:
> ps-clk-frequency is platform specific setting and shouldn't be the part
> of DTSI.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> Sync with mainline.
>
> ---
> arch/arm/dts/zynq-7000.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index a1de993b9812..095c0f67e167 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -241,7 +241,6 @@
> clkc: clkc at 100 {
> #clock-cells = <1>;
> compatible = "xlnx,ps7-clkc";
> - ps-clk-frequency = <33333333>;
If you remove it here, shouldn't it be added in the board dts files at
the same time (the Linux implementation may default to 33MHz, but that
is implementation and not guaranteed according to the bindings)?
S?ren
^ permalink raw reply [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency
2015-07-22 15:51 ` Sören Brinkmann
@ 2015-07-24 12:47 ` Michal Simek
0 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-24 12:47 UTC (permalink / raw)
To: u-boot
On 07/22/2015 05:51 PM, S?ren Brinkmann wrote:
> On Wed, 2015-07-22 at 05:38PM +0200, Michal Simek wrote:
>> ps-clk-frequency is platform specific setting and shouldn't be the part
>> of DTSI.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> Sync with mainline.
>>
>> ---
>> arch/arm/dts/zynq-7000.dtsi | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
>> index a1de993b9812..095c0f67e167 100644
>> --- a/arch/arm/dts/zynq-7000.dtsi
>> +++ b/arch/arm/dts/zynq-7000.dtsi
>> @@ -241,7 +241,6 @@
>> clkc: clkc at 100 {
>> #clock-cells = <1>;
>> compatible = "xlnx,ps7-clkc";
>> - ps-clk-frequency = <33333333>;
>
> If you remove it here, shouldn't it be added in the board dts files at
> the same time (the Linux implementation may default to 33MHz, but that
> is implementation and not guaranteed according to the bindings)?
If you look it is already there and platform with full description are
rewriting it. Platform without full description are useless for Linux
anyway.
Thanks,
Michal
^ permalink raw reply [flat|nested] 22+ messages in thread
* [U-Boot] [PATCH 16/19] ARM: zynq: DT: Add missing interrupt for L2 pl310
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (13 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 15/19] ARM: zynq: DT: Get rid of ps-clk-frequency Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 17/19] ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys Michal Simek
` (2 subsequent siblings)
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Add pl310 interrupt to the Zynq devicetree.
Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynq-7000.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 095c0f67e167..0b62cb093658 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -135,6 +135,7 @@
L2: cache-controller at f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
+ interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 17/19] ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (14 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 16/19] ARM: zynq: DT: Add missing interrupt for L2 pl310 Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 18/19] ARM: zynq: DT: Update zc770 dtses Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 19/19] ARM: zynq: Add support for zc770-xm011 Michal Simek
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Adds the two MIO connected pushbuttons on the zc702 board to the
devicetree as a single multi-key device for us with the gpio-keys driver.
Signed-off-by: Ezra Savard <ezra.savard@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynq-zc702.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 1c879846813e..6691a8de247d 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -29,6 +29,27 @@
stdout-path = "serial0:115200n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw14 {
+ label = "sw14";
+ gpios = <&gpio0 12 0>;
+ linux,code = <108>; /* down */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ sw13 {
+ label = "sw13";
+ gpios = <&gpio0 14 0>;
+ linux,code = <103>; /* up */
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
leds {
compatible = "gpio-leds";
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 18/19] ARM: zynq: DT: Update zc770 dtses
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (15 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 17/19] ARM: zynq: DT: Add zc702 pushbuttons to DT as gpio-keys Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
2015-07-22 15:38 ` [U-Boot] [PATCH 19/19] ARM: zynq: Add support for zc770-xm011 Michal Simek
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Platform DTSes are missing content needed for platform to be able to use
OF binding and DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/zynq-zc770-xm010.dts | 75 ++++++++++++++++++++++++++++++++++++---
arch/arm/dts/zynq-zc770-xm012.dts | 51 +++++++++++++++++++++++---
arch/arm/dts/zynq-zc770-xm013.dts | 62 ++++++++++++++++++++++++++++++--
3 files changed, 176 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index bf107e308a6a..da3a182ea1e1 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -1,7 +1,7 @@
/*
* Xilinx ZC770 XM010 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,20 +9,85 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
aliases {
+ ethernet0 = &gem0;
+ i2c0 = &i2c0;
serial0 = &uart1;
- spi1 = &spi1;
+ spi0 = &spi1;
};
- memory {
+ chosen {
+ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
+ };
+
+ memory at 0 {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
};
};
&spi1 {
status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ flash at 0 {
+ compatible = "sst25wf080";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition at test {
+ label = "spi-flash";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy at 7 {
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom at 52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
+ };
+
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
};
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 127a6619c631..f8cc5039d6b7 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -1,7 +1,7 @@
/*
* Xilinx ZC770 XM012 board DTS
*
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,15 +9,58 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
serial0 = &uart1;
+ spi0 = &spi1;
};
- memory {
+ chosen {
+ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
+ };
+
+ memory at 0 {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
+&can1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom at 52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom at 52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
};
};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index c61c7e7592f8..436a8cd1b9a9 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -9,15 +9,71 @@
#include "zynq-7000.dtsi"
/ {
- model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
aliases {
+ ethernet0 = &gem1;
+ i2c0 = &i2c1;
serial0 = &uart0;
+ spi0 = &spi0;
};
- memory {
+ chosen {
+ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+ linux,stdout-path = &uart0;
+ stdout-path = &uart0;
+ };
+
+ memory at 0 {
device_type = "memory";
- reg = <0 0x40000000>;
+ reg = <0x0 0x40000000>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ eeprom: at25 at 0 {
+ at25,byte-len = <8192>;
+ at25,addr-mode = <2>;
+ at25,page-size = <32>;
+
+ compatible = "atmel,at25";
+ reg = <2>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy at 7 {
+ reg = <7>;
};
};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ si570: clock-generator at 55 {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x55>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [U-Boot] [PATCH 19/19] ARM: zynq: Add support for zc770-xm011
2015-07-22 15:37 [U-Boot] [PATCH 01/19] ARM: zynq: DT: Use the right names for nodes Michal Simek
` (16 preceding siblings ...)
2015-07-22 15:38 ` [U-Boot] [PATCH 18/19] ARM: zynq: DT: Update zc770 dtses Michal Simek
@ 2015-07-22 15:38 ` Michal Simek
17 siblings, 0 replies; 22+ messages in thread
From: Michal Simek @ 2015-07-22 15:38 UTC (permalink / raw)
To: u-boot
Add xm011 DTS file and related configs and configurations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-zc770-xm011.dts | 65 ++++++++++++++++++++++++++++++++++++++
configs/zynq_zc770_xm011_defconfig | 13 ++++++++
include/configs/zynq_zc770.h | 3 ++
4 files changed, 82 insertions(+)
create mode 100644 arch/arm/dts/zynq-zc770-xm011.dts
create mode 100644 configs/zynq_zc770_xm011_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8ebd6934320b..06fbd8b0af20 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
zynq-zc770-xm010.dtb \
+ zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts
new file mode 100644
index 000000000000..d38c8201353c
--- /dev/null
+++ b/arch/arm/dts/zynq-zc770-xm011.dts
@@ -0,0 +1,65 @@
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+/ {
+ compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+
+ aliases {
+ i2c0 = &i2c1;
+ serial0 = &uart1;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+ linux,stdout-path = &uart1;
+ stdout-path = &uart1;
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ usb_phy1: phy1 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+};
+
+&can0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ m24c02_eeprom at 52 {
+ compatible = "at,24c02";
+ reg = <0x52>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy1>;
+};
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
new file mode 100644
index 000000000000..8f9221db85e3
--- /dev/null
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_TARGET_ZYNQ_ZC770=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/zynq_zc770.h b/include/configs/zynq_zc770.h
index 16b904743f1e..7a1b8729e5b1 100644
--- a/include/configs/zynq_zc770.h
+++ b/include/configs/zynq_zc770.h
@@ -21,6 +21,9 @@
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_SPI
+#elif defined(CONFIG_ZC770_XM011)
+# define CONFIG_ZYNQ_SERIAL_UART1
+
#elif defined(CONFIG_ZC770_XM012)
# define CONFIG_ZYNQ_SERIAL_UART1
# undef CONFIG_SYS_NO_FLASH
--
2.3.5
^ permalink raw reply related [flat|nested] 22+ messages in thread