[U-Boot] [PATCH v3 01/25] rockchip: Add serial support

Simon Glass
2015-06-23T23:28:46Z

Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Update clock rate to always be 24MHz

Changes in v2: None

drivers/serial/Kconfig | 9 +++++++++
drivers/serial/Makefile | 1 +
drivers/serial/serial_rockchip.c | 43 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 53 insertions(+)
create mode 100644 drivers/serial/serial_rockchip.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 4829284..3544d66 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -76,6 +76,15 @@ config DEBUG_UART_SHIFT
value. Use this value to specify the shift to use, where 0=byte
registers, 2=32-bit word registers, etc.

+config ROCKCHIP_SERIAL
+ bool "Rockchip on-chip UART support"
+ depends on ARCH_UNIPHIER && DM_SERIAL
+ help
+ Select this to enable a debug UART for Rockchip devices. This uses
+ the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
+ your board config header. The clock input is automatically set to
+ use the oscillator (24MHz).
+
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX && DM
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d183eed..b926b49 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
new file mode 100644
index 0000000..0e7bbfc
--- /dev/null
+++ b/drivers/serial/serial_rockchip.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rockchip_serial_ids[] = {
+ { .compatible = "rockchip,rk3288-uart" },
+ { }
+};
+
+static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+
+ /* Do all Rockchip parts use 24MHz? */
+ plat->clock = 24 * 1000000;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+ .name = "serial_rockchip",
+ .id = UCLASS_SERIAL,
+ .of_match = rockchip_serial_ids,
+ .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.4.3.573.g4eafbef