From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Tue, 28 Jul 2015 14:21:50 -0500
Subject: [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge
	reset handling
In-Reply-To: <1438030335-10631-13-git-send-email-marex@denx.de>
References: <1438030335-10631-1-git-send-email-marex@denx.de>
 <1438030335-10631-13-git-send-email-marex@denx.de>
Message-ID: <55B7D64E.7000903@opensource.altera.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de



On 7/27/15 3:49 PM, Marek Vasut wrote:
> The current bridge reset code, which de-asserted the bridge reset,
> was activelly polling whether the FPGA is programmed and ready and

s/activelly/actively

Again...only comment for this patch, no need to resend.

Dinh