From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 31 Jul 2015 08:51:26 -0700 Subject: [U-Boot] [PATCH 1/3][v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 In-Reply-To: <1434431160-25055-1-git-send-email-aneesh.bansal@freescale.com> References: <1434431160-25055-1-git-send-email-aneesh.bansal@freescale.com> Message-ID: <55BB997E.9000805@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 06/15/2015 10:06 PM, Aneesh Bansal wrote: > Secure Boot Target is added for NAND for P3041. > Changes: > In PowerPC, the core begins execution from address 0xFFFFFFFC. > In case of secure boot, this default address maps to Boot ROM. > The Boot ROM code requires that the bootloader(U-boot) must lie > in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. > > In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is > configured as SRAM. U-Boot binary will be located on SRAM configured > at address 0xBFF00000. > In the U-Boot code, TLB entries are created to map the virtual address > 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. > > Signed-off-by: Saksham Jain > Signed-off-by: Ruchika Gupta > Signed-off-by: Aneesh Bansal > --- > Changes in v7: > Created TLB entry to map virtual address 0xFFF00000 to physical address > 0xBFF00000 as per discussion. > Applied to u-boot-mpc85xx master after adding CONFIG_SPI_FLASH to defconfig. Thanks. York