[U-Boot] [PATCH 2/3][[v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

[U-Boot] [PATCH 2/3][[v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

[Aneesh Bansal]

Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
---
Changes in v7:
Patchset created.
TEXT BASE is defined as 0xFFF40000 as per new design.

 board/freescale/corenet_ds/MAINTAINERS     | 2 ++
 configs/P5020DS_NAND_SECURE_BOOT_defconfig | 4 ++++
 configs/P5040DS_NAND_SECURE_BOOT_defconfig | 4 ++++
 3 files changed, 10 insertions(+)
 create mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig
 create mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig

diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 6855446..73b0553 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD
 M:	Aneesh Bansal <aneesh.bansal@freescale.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..5edfe45
--- /dev/null
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5020DS=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000..f33d236
--- /dev/null
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5040DS=y
-- 
1.8.1.4

[U-Boot] [PATCH 2/3][[v7] powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

[York Sun]

On 06/15/2015 10:06 PM, Aneesh Bansal wrote:
> Secure Boot Target is added for NAND for P5020 and P5040.
> The Secure boot target has already been added for P3041 by
> enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.
> 
> The targets for P5020 and P5040 are added in the same manner.
> 
> Signed-off-by: Saksham Jain <saksham@freescale.com>
> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
> ---
> Changes in v7:
> Patchset created.
> TEXT BASE is defined as 0xFFF40000 as per new design.
> 

Applied to u-boot-mpc85xx master after adding CONFIG_SPI_FLASH to defconfig.

Thanks.

York