From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 02 Aug 2015 10:46:52 +0200 Subject: [U-Boot] [PATCH V5 4/6] imx: mx6qp Enable PRG clock for IPU In-Reply-To: <1436585927-18677-4-git-send-email-Peng.Fan@freescale.com> References: <1436585927-18677-1-git-send-email-Peng.Fan@freescale.com> <1436585927-18677-4-git-send-email-Peng.Fan@freescale.com> Message-ID: <55BDD8FC.5010109@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/07/2015 05:38, Peng Fan wrote: > The i.MX6DQP has a PRG module, need to enable its clock for using IPU. > > Signed-off-by: Peng Fan > Signed-off-by: Brown Oliver > Signed-off-by: Ye.Li > Reviewed-by: Fabio Estevam > Acked-by: Stefano Babic > --- > > Changes v5: > Add Stefano's Acked-by > > Changes v4: > Take Fabio's suggestion, use setbits_le32. Add Fabio's Reviewed-by > > Changes v3: > Remove ipu qos settings > > Changes v2: > 1. runtime check > 2. introduce ipu qos settings for better performance > > arch/arm/cpu/armv7/mx6/clock.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index cd4bfdd..3e94472 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -853,6 +853,11 @@ void enable_ipu_clock(void) > reg = readl(&mxc_ccm->CCGR3); > reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; > writel(reg, &mxc_ccm->CCGR3); > + > + if (is_mx6dqp()) { > + setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); > + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); > + } > } > #endif > /***************************************************/ > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================