From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers head file
Date: Sun, 02 Aug 2015 11:15:42 +0200 [thread overview]
Message-ID: <55BDDFBE.2010407@denx.de> (raw)
In-Reply-To: <1437391715-1344-4-git-send-email-Peng.Fan@freescale.com>
On 20/07/2015 13:28, Peng Fan wrote:
> 1. Update imx register base address for i.MX6UL.
> 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
> 3. Remove #ifdef for register addresses that equal to
> "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
> 4. According fuse map, complete fuse_bank4_regs.
> 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
> because we can use runtime check
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> ---
>
> Changes v3:
> Taking Marek's suggestion, fix the WDOG3_BASE_ADDRESS for assembler usage.
>
> Changes v2:
> split CONFIG_SYS_CACHELINE_SIZE part into another patch
>
> arch/arm/include/asm/arch-mx6/imx-regs.h | 60 +++++++++++++++++++-------------
> 1 file changed, 35 insertions(+), 25 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 35a324c..d8b5d6f 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -19,7 +19,7 @@
> #define GPU_2D_ARB_END_ADDR 0x02203FFF
> #define OPENVG_ARB_BASE_ADDR 0x02204000
> #define OPENVG_ARB_END_ADDR 0x02207FFF
> -#elif CONFIG_MX6SX
> +#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define CAAM_ARB_BASE_ADDR 0x00100000
> #define CAAM_ARB_END_ADDR 0x00107FFF
> #define GPU_ARB_BASE_ADDR 0x01800000
> @@ -28,10 +28,6 @@
> #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
> #define M4_BOOTROM_BASE_ADDR 0x007F8000
>
> -#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
> -#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
> -#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
> -
> #else
> #define CAAM_ARB_BASE_ADDR 0x00100000
> #define CAAM_ARB_END_ADDR 0x00103FFF
> @@ -52,13 +48,13 @@
> #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
>
> /* GPV - PL301 configuration ports */
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define GPV2_BASE_ADDR 0x00D00000
> #else
> #define GPV2_BASE_ADDR 0x00200000
> #endif
>
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define GPV3_BASE_ADDR 0x00E00000
> #define GPV4_BASE_ADDR 0x00F00000
> #define GPV5_BASE_ADDR 0x01000000
> @@ -87,15 +83,21 @@
> #define AIPS1_ARB_END_ADDR 0x020FFFFF
> #define AIPS2_ARB_BASE_ADDR 0x02100000
> #define AIPS2_ARB_END_ADDR 0x021FFFFF
> -#ifdef CONFIG_MX6SX
> +/* AIPS3 only on i.MX6SX */
> #define AIPS3_ARB_BASE_ADDR 0x02200000
> #define AIPS3_ARB_END_ADDR 0x022FFFFF
> +#ifdef CONFIG_MX6SX
> #define WEIM_ARB_BASE_ADDR 0x50000000
> #define WEIM_ARB_END_ADDR 0x57FFFFFF
> #define QSPI0_AMBA_BASE 0x60000000
> #define QSPI0_AMBA_END 0x6FFFFFFF
> #define QSPI1_AMBA_BASE 0x70000000
> #define QSPI1_AMBA_END 0x7FFFFFFF
> +#elif defined(CONFIG_MX6UL)
> +#define WEIM_ARB_BASE_ADDR 0x50000000
> +#define WEIM_ARB_END_ADDR 0x57FFFFFF
> +#define QSPI0_AMBA_BASE 0x60000000
> +#define QSPI0_AMBA_END 0x6FFFFFFF
> #else
> #define SATA_ARB_BASE_ADDR 0x02200000
> #define SATA_ARB_END_ADDR 0x02203FFF
> @@ -111,7 +113,7 @@
> #define WEIM_ARB_END_ADDR 0x0FFFFFFF
> #endif
>
> -#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define MMDC0_ARB_BASE_ADDR 0x80000000
> #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
> #define MMDC1_ARB_BASE_ADDR 0xC0000000
> @@ -238,13 +240,16 @@
> #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
> #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
> #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
> -#ifdef CONFIG_MX6SL
> +/* i.MX6SL */
> #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> -#elif CONFIG_MX6SX
> -#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> +#ifdef CONFIG_MX6UL
> +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
> #else
> -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> +/* i.MX6SX */
> +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> #endif
> +/* i.MX6DQ/SDL */
> +#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
>
> #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
> #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
> @@ -257,22 +262,21 @@
> #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
> #endif
> #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
> -#ifdef CONFIG_MX6SX
> +#ifdef CONFIG_MX6UL
> +#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> +#elif defined(CONFIG_MX6SX)
> #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> -#else
> -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> -#endif
> #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> -#ifdef CONFIG_MX6SX
> #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #else
> +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #endif
> +#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
> #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
> #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
> @@ -296,7 +300,6 @@
> #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
> #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
> #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
> -#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
> #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
> #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
> @@ -308,12 +311,17 @@
> #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
> #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
> #endif
> +#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> +
> +/* only for i.MX6SX/UL */
> +#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
> + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
>
> #define CHIP_REV_1_0 0x10
> #define CHIP_REV_1_2 0x12
> #define CHIP_REV_1_5 0x15
> #define CHIP_REV_2_0 0x20
> -#ifndef CONFIG_MX6SX
> +#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> #define IRAM_SIZE 0x00040000
> #else
> #define IRAM_SIZE 0x00020000
> @@ -451,7 +459,7 @@ struct src {
>
>
> struct iomuxc {
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> u8 reserved[0x4000];
> #endif
> u32 gpr[14];
> @@ -577,7 +585,7 @@ struct cspi_regs {
> #define MXC_CSPICON_POL 4 /* SCLK polarity */
> #define MXC_CSPICON_SSPOL 12 /* SS polarity */
> #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
> -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
> +#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
> #define MXC_SPI_BASE_ADDRESSES \
> ECSPI1_BASE_ADDR, \
> ECSPI2_BASE_ADDR, \
> @@ -661,7 +669,7 @@ struct fuse_bank1_regs {
> u32 rsvd7[3];
> };
>
> -#ifdef CONFIG_MX6SX
> +#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
> @@ -674,7 +682,9 @@ struct fuse_bank4_regs {
> u32 mac_addr2;
> u32 rsvd4[7];
> u32 gp1;
> - u32 rsvd5[7];
> + u32 rsvd5[3];
> + u32 gp2;
> + u32 rsvd6[3];
> };
> #else
> struct fuse_bank4_regs {
>
Applied to u-boot-imx, thanks !
Best regards,
Stefano Babic
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next prev parent reply other threads:[~2015-08-02 9:15 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-20 11:28 [U-Boot] [PATCH v3 00/15] imx: Add i.MX6UL and basic board support Peng Fan
2015-07-20 11:28 ` [U-Boot] [PATCH v3 01/15] imx: mx6ul: Add i.MX6UL CPU type Peng Fan
2015-08-02 9:05 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 02/15] imx: mx6ul: Add pins IOMUX head file Peng Fan
2015-08-02 9:06 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 03/15] imx: mx6ul: Update imx registers " Peng Fan
2015-07-20 18:39 ` Marek Vasut
2015-08-02 9:07 ` Stefano Babic
2015-08-02 9:15 ` Stefano Babic [this message]
2015-07-20 11:28 ` [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Peng Fan
2015-08-02 9:15 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 05/15] imx-common: timer: add i.MX6UL support Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 06/15] imx: mx6ul remove errata for i.MX6UL Peng Fan
2015-08-02 9:16 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 07/15] imx:mx6ul add clock support Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 09/15] imx: mx6ul update soc related settings Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 10/15] imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 11/15] mxc: gpio add i.MX6UL support Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 12/15] mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL Peng Fan
2015-08-02 9:17 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 13/15] imx:mx6ul add dram spl configuration and header file Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 14/15] imx: imx6_spl add mx6ul support Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-07-20 11:28 ` [U-Boot] [PATCH v3 15/15] imx: mx6ul_14x14_evk add basic board support Peng Fan
2015-08-02 9:18 ` Stefano Babic
2015-08-10 16:22 ` Fabio Estevam
2015-08-11 0:13 ` Peng Fan
2015-08-11 10:31 ` Fabio Estevam
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