From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 02 Aug 2015 11:15:56 +0200 Subject: [U-Boot] [PATCH v3 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL In-Reply-To: <1437391715-1344-5-git-send-email-Peng.Fan@freescale.com> References: <1437391715-1344-1-git-send-email-Peng.Fan@freescale.com> <1437391715-1344-5-git-send-email-Peng.Fan@freescale.com> Message-ID: <55BDDFCC.9070508@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 20/07/2015 13:28, Peng Fan wrote: > Since i.MX6UL's cache line size is 64bytes, need to > define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. > > Signed-off-by: Peng Fan > --- > > Changes v3: > none > Changes v2: > new patch, splitted from patch 03/15. > > arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h > index d8b5d6f..4d84a9b 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -9,7 +9,11 @@ > > #define ARCH_MXC > > +#ifdef CONFIG_MX6UL > +#define CONFIG_SYS_CACHELINE_SIZE 64 > +#else > #define CONFIG_SYS_CACHELINE_SIZE 32 > +#endif > > #define ROMCP_ARB_BASE_ADDR 0x00000000 > #define ROMCP_ARB_END_ADDR 0x000FFFFF > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================