From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 02 Aug 2015 11:17:14 +0200 Subject: [U-Boot] [PATCH v3 08/15] imx: mx6ul select SYS_L2CACHE_OFF In-Reply-To: <1437391715-1344-9-git-send-email-Peng.Fan@freescale.com> References: <1437391715-1344-1-git-send-email-Peng.Fan@freescale.com> <1437391715-1344-9-git-send-email-Peng.Fan@freescale.com> Message-ID: <55BDE01A.9050104@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 20/07/2015 13:28, Peng Fan wrote: > i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 > chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. > There is on specific switch for on/off L2 Cache, so default select > SYS_L2CACHE_OFF. > > Signed-off-by: Peng Fan > --- > > Changes v3: > none > > Changes v2: > refine commit msg. > > arch/arm/cpu/armv7/mx6/Kconfig | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig > index 10908c4..fceba27 100644 > --- a/arch/arm/cpu/armv7/mx6/Kconfig > +++ b/arch/arm/cpu/armv7/mx6/Kconfig > @@ -25,6 +25,10 @@ config MX6SL > config MX6SX > bool > > +config MX6UL > + select SYS_L2CACHE_OFF > + bool > + > choice > prompt "MX6 board select" > optional > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================