* [U-Boot] [PATCH 01/15] ddr: altera: sequencer: Move qts-generated files to board dir
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:54 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 02/15] ddr: altera: sequencer: Clean up mach/sdram.h Marek Vasut
` (13 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.
Signed-off-by: Marek Vasut <marex@denx.de>
---
.../altera => board/altera/socfpga/qts}/sequencer_auto.h | 0
.../altera/socfpga/qts}/sequencer_auto_ac_init.h | 0
.../altera/socfpga/qts}/sequencer_auto_inst_init.h | 0
.../altera => board/altera/socfpga/qts}/sequencer_defines.h | 0
drivers/ddr/altera/sequencer.c | 13 +++++++++----
5 files changed, 9 insertions(+), 4 deletions(-)
rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto.h (100%)
rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto_ac_init.h (100%)
rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto_inst_init.h (100%)
rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_defines.h (100%)
diff --git a/drivers/ddr/altera/sequencer_auto.h b/board/altera/socfpga/qts/sequencer_auto.h
similarity index 100%
rename from drivers/ddr/altera/sequencer_auto.h
rename to board/altera/socfpga/qts/sequencer_auto.h
diff --git a/drivers/ddr/altera/sequencer_auto_ac_init.h b/board/altera/socfpga/qts/sequencer_auto_ac_init.h
similarity index 100%
rename from drivers/ddr/altera/sequencer_auto_ac_init.h
rename to board/altera/socfpga/qts/sequencer_auto_ac_init.h
diff --git a/drivers/ddr/altera/sequencer_auto_inst_init.h b/board/altera/socfpga/qts/sequencer_auto_inst_init.h
similarity index 100%
rename from drivers/ddr/altera/sequencer_auto_inst_init.h
rename to board/altera/socfpga/qts/sequencer_auto_inst_init.h
diff --git a/drivers/ddr/altera/sequencer_defines.h b/board/altera/socfpga/qts/sequencer_defines.h
similarity index 100%
rename from drivers/ddr/altera/sequencer_defines.h
rename to board/altera/socfpga/qts/sequencer_defines.h
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 37f7354..bc2e457 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -9,10 +9,15 @@
#include <asm/arch/sdram.h>
#include <errno.h>
#include "sequencer.h"
-#include "sequencer_auto.h"
-#include "sequencer_auto_ac_init.h"
-#include "sequencer_auto_inst_init.h"
-#include "sequencer_defines.h"
+
+/*
+ * FIXME: This path is temporary until the SDRAM driver gets
+ * a proper thorough cleanup.
+ */
+#include "../../../board/altera/socfpga/qts/sequencer_auto.h"
+#include "../../../board/altera/socfpga/qts/sequencer_auto_ac_init.h"
+#include "../../../board/altera/socfpga/qts/sequencer_auto_inst_init.h"
+#include "../../../board/altera/socfpga/qts/sequencer_defines.h"
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 01/15] ddr: altera: sequencer: Move qts-generated files to board dir
2015-08-02 23:21 ` [U-Boot] [PATCH 01/15] ddr: altera: sequencer: Move qts-generated files to board dir Marek Vasut
@ 2015-08-03 15:54 ` Dinh Nguyen
0 siblings, 0 replies; 32+ messages in thread
From: Dinh Nguyen @ 2015-08-03 15:54 UTC (permalink / raw)
To: u-boot
On 08/02/2015 06:21 PM, Marek Vasut wrote:
> Move the files generated by QTS into the board directory, they should not
> be part of the driver files at all.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> .../altera => board/altera/socfpga/qts}/sequencer_auto.h | 0
> .../altera/socfpga/qts}/sequencer_auto_ac_init.h | 0
> .../altera/socfpga/qts}/sequencer_auto_inst_init.h | 0
> .../altera => board/altera/socfpga/qts}/sequencer_defines.h | 0
> drivers/ddr/altera/sequencer.c | 13 +++++++++----
> 5 files changed, 9 insertions(+), 4 deletions(-)
> rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto.h (100%)
> rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto_ac_init.h (100%)
> rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_auto_inst_init.h (100%)
> rename {drivers/ddr/altera => board/altera/socfpga/qts}/sequencer_defines.h (100%)
>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Thanks,
Dinh
^ permalink raw reply [flat|nested] 32+ messages in thread
* [U-Boot] [PATCH 02/15] ddr: altera: sequencer: Clean up mach/sdram.h
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
2015-08-02 23:21 ` [U-Boot] [PATCH 01/15] ddr: altera: sequencer: Move qts-generated files to board dir Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:55 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 03/15] ddr: altera: sequencer: Zap unused params and macros Marek Vasut
` (12 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Zap non-existent functions and place function prototypes at the
beginning of the header file.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 0cebd50..c139a28 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -12,7 +12,7 @@ unsigned long sdram_calculate_size(void);
int sdram_mmr_init_full(unsigned int sdr_phy_reg);
int sdram_calibration_full(void);
-extern int sdram_calibration(void);
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@@ -113,8 +113,6 @@ struct socfpga_sdram_config {
u32 phy_ctrl0;
};
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
-
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 03/15] ddr: altera: sequencer: Zap unused params and macros
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
2015-08-02 23:21 ` [U-Boot] [PATCH 01/15] ddr: altera: sequencer: Move qts-generated files to board dir Marek Vasut
2015-08-02 23:21 ` [U-Boot] [PATCH 02/15] ddr: altera: sequencer: Clean up mach/sdram.h Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:55 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 04/15] ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS Marek Vasut
` (11 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
These parameters are not used in the code, zap them and the
macros which are used by them as well.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 49 +-----------------------------------------
drivers/ddr/altera/sequencer.h | 31 ++++----------------------
2 files changed, 5 insertions(+), 75 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index bc2e457..06a3bf6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -83,7 +83,6 @@ uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
struct gbl_type *gbl;
struct param_type *param;
-uint32_t curr_shadow_reg;
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
@@ -151,9 +150,6 @@ static void phy_mgr_initialize(void)
param->write_correct_mask_vg = (1 << ratio) - 1;
param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
- ratio = RW_MGR_MEM_DATA_WIDTH /
- RW_MGR_MEM_DATA_MASK_WIDTH;
- param->dm_correct_mask = (1 << ratio) - 1;
}
/**
@@ -885,11 +881,6 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
u32 r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
-
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
@@ -1192,10 +1183,6 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
*bit_chk = param->write_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
- /* Request to skip the rank */
- if (param->skip_ranks[r])
- continue;
-
/* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
@@ -1266,10 +1253,6 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
- /* Request to skip the rank */
- if (param->skip_ranks[r])
- continue;
-
/* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
@@ -1333,10 +1316,6 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
debug("%s:%d\n", __func__, __LINE__);
for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
-
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
@@ -1403,10 +1382,6 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
*bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
-
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
@@ -2662,10 +2637,6 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
for (rank_bgn = 0, sr = 0;
rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- /* Check if this set of ranks should be skipped entirely. */
- if (param->skip_shadow_regs[sr])
- continue;
-
ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
test_bgn,
use_read_test,
@@ -3159,10 +3130,6 @@ static void mem_precharge_and_activate(void)
int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- /* Test if the rank should be skipped. */
- if (param->skip_ranks[r])
- continue;
-
/* Set rank. */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
@@ -3380,7 +3347,7 @@ static uint32_t mem_calibrate(void)
*/
scc_mgr_zero_all();
- run_groups = ~param->skip_groups;
+ run_groups = ~0;
for (write_group = 0, write_test_bgn = 0; write_group
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
@@ -3432,13 +3399,6 @@ static uint32_t mem_calibrate(void)
if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
continue;
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (param->skip_shadow_regs[sr])
- continue;
-
/* Calibrate WRITEs */
if (!rw_mgr_mem_calibrate_writes(rank_bgn,
write_group, write_test_bgn))
@@ -3489,13 +3449,6 @@ grp_failed: /* A group failed, increment the counter. */
if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
continue;
- /*
- * If we're skipping groups as part of debug,
- * don't calibrate LFIFO.
- */
- if (param->skip_groups != 0)
- continue;
-
/* Calibrate the LFIFO */
if (!rw_mgr_mem_calibrate_lfifo())
return 0;
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 3e4152f..3ecd733 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -66,14 +66,6 @@
#define CAL_SUBSTAGE_READ_LATENCY 1
#define CAL_SUBSTAGE_REFRESH 1
-#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
-#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
- RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
- RW_MGR_MEM_IF_READ_DQS_WIDTH)
-#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
-#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
-
/* length of VFIFO, from SW_MACROS */
#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
@@ -212,25 +204,10 @@ struct socfpga_sdr_reg_file {
/* parameter variable holder */
struct param_type {
- uint32_t dm_correct_mask;
- uint32_t read_correct_mask;
- uint32_t read_correct_mask_vg;
- uint32_t write_correct_mask;
- uint32_t write_correct_mask_vg;
-
- /* set a particular entry to 1 if we need to skip a particular rank */
-
- uint32_t skip_ranks[MAX_RANKS];
-
- /* set a particular entry to 1 if we need to skip a particular group */
-
- uint32_t skip_groups;
-
- /* set a particular entry to 1 if the shadow register
- (which represents a set of ranks) needs to be skipped */
-
- uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
-
+ u32 read_correct_mask;
+ u32 read_correct_mask_vg;
+ u32 write_correct_mask;
+ u32 write_correct_mask_vg;
};
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 04/15] ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (2 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 03/15] ddr: altera: sequencer: Zap unused params and macros Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:55 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 05/15] ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init Marek Vasut
` (10 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
This is defined in the QTS-generated headers, so it must not be
re-defined in sequencer.h .
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 3ecd733..f621e14 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -23,7 +23,6 @@
#define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
#define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
#define NUM_SHADOW_REGS 1
#define RW_MGR_RANK_NONE 0xFF
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 05/15] ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (3 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 04/15] ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:53 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 06/15] ddr: altera: sequencer: Wrap RW_MGR_* macros Marek Vasut
` (9 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace polution again.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 3 +++
board/altera/socfpga/wrap_sdram_config.c | 15 +++++++++++++++
drivers/ddr/altera/sequencer.c | 14 ++++++++------
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index c139a28..901cd9b 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -14,6 +14,9 @@ int sdram_calibration_full(void);
const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
struct socfpga_sdr_ctrl {
diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c
index c70854e..d87bec0 100644
--- a/board/altera/socfpga/wrap_sdram_config.c
+++ b/board/altera/socfpga/wrap_sdram_config.c
@@ -10,6 +10,9 @@
/* QTS output file. */
#include "qts/sdram_config.h"
+#include "qts/sequencer_auto_ac_init.h"
+#include "qts/sequencer_auto_inst_init.h"
+
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
@@ -183,3 +186,15 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
{
return &sdram_config;
}
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
+{
+ *init = ac_rom_init;
+ *nelem = ARRAY_SIZE(ac_rom_init);
+}
+
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
+{
+ *init = inst_rom_init;
+ *nelem = ARRAY_SIZE(inst_rom_init);
+}
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 06a3bf6..31e339b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -15,8 +15,6 @@
* a proper thorough cleanup.
*/
#include "../../../board/altera/socfpga/qts/sequencer_auto.h"
-#include "../../../board/altera/socfpga/qts/sequencer_auto_ac_init.h"
-#include "../../../board/altera/socfpga/qts/sequencer_auto_inst_init.h"
#include "../../../board/altera/socfpga/qts/sequencer_defines.h"
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
@@ -3561,15 +3559,19 @@ static void debug_mem_calibrate(int pass)
*/
static void hc_initialize_rom_data(void)
{
+ unsigned int nelem = 0;
+ const u32 *rom_init;
u32 i, addr;
+ socfpga_get_seq_inst_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
- writel(inst_rom_init[i], addr + (i << 2));
+ for (i = 0; i < nelem; i++)
+ writel(rom_init[i], addr + (i << 2));
+ socfpga_get_seq_ac_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
- writel(ac_rom_init[i], addr + (i << 2));
+ for (i = 0; i < nelem; i++)
+ writel(rom_init[i], addr + (i << 2));
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 06/15] ddr: altera: sequencer: Wrap RW_MGR_* macros
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (4 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 05/15] ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:57 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 07/15] ddr: altera: sequencer: Pluck out RW_MGR_* macros from code Marek Vasut
` (8 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the polution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 64 ++++++++++++++++++++++++++
board/altera/socfpga/wrap_sdram_config.c | 72 ++++++++++++++++++++++++++++++
drivers/ddr/altera/sequencer.c | 4 ++
3 files changed, 140 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 901cd9b..eb40934 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -16,6 +16,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@@ -116,6 +117,69 @@ struct socfpga_sdram_config {
u32 phy_ctrl0;
};
+struct socfpga_sdram_rw_mgr_config {
+ u8 activate_0_and_1;
+ u8 activate_0_and_1_wait1;
+ u8 activate_0_and_1_wait2;
+ u8 activate_1;
+ u8 clear_dqs_enable;
+ u8 guaranteed_read;
+ u8 guaranteed_read_cont;
+ u8 guaranteed_write;
+ u8 guaranteed_write_wait0;
+ u8 guaranteed_write_wait1;
+ u8 guaranteed_write_wait2;
+ u8 guaranteed_write_wait3;
+ u8 idle;
+ u8 idle_loop1;
+ u8 idle_loop2;
+ u8 init_reset_0_cke_0;
+ u8 init_reset_1_cke_0;
+ u8 lfsr_wr_rd_bank_0;
+ u8 lfsr_wr_rd_bank_0_data;
+ u8 lfsr_wr_rd_bank_0_dqs;
+ u8 lfsr_wr_rd_bank_0_nop;
+ u8 lfsr_wr_rd_bank_0_wait;
+ u8 lfsr_wr_rd_bank_0_wl_1;
+ u8 lfsr_wr_rd_dm_bank_0;
+ u8 lfsr_wr_rd_dm_bank_0_data;
+ u8 lfsr_wr_rd_dm_bank_0_dqs;
+ u8 lfsr_wr_rd_dm_bank_0_nop;
+ u8 lfsr_wr_rd_dm_bank_0_wait;
+ u8 lfsr_wr_rd_dm_bank_0_wl_1;
+ u8 mrs0_dll_reset;
+ u8 mrs0_dll_reset_mirr;
+ u8 mrs0_user;
+ u8 mrs0_user_mirr;
+ u8 mrs1;
+ u8 mrs1_mirr;
+ u8 mrs2;
+ u8 mrs2_mirr;
+ u8 mrs3;
+ u8 mrs3_mirr;
+ u8 precharge_all;
+ u8 read_b2b;
+ u8 read_b2b_wait1;
+ u8 read_b2b_wait2;
+ u8 refresh_all;
+ u8 rreturn;
+ u8 sgle_read;
+ u8 zqcl;
+
+ u8 true_mem_data_mask_width;
+ u8 mem_address_mirroring;
+ u8 mem_data_mask_width;
+ u8 mem_data_width;
+ u8 mem_dq_per_read_dqs;
+ u8 mem_dq_per_write_dqs;
+ u8 mem_if_read_dqs_width;
+ u8 mem_if_write_dqs_width;
+ u8 mem_number_of_cs_per_dimm;
+ u8 mem_number_of_ranks;
+ u8 mem_virtual_groups_per_read_dqs;
+ u8 mem_virtual_groups_per_write_dqs;
+};
+
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c
index d87bec0..5fe1571 100644
--- a/board/altera/socfpga/wrap_sdram_config.c
+++ b/board/altera/socfpga/wrap_sdram_config.c
@@ -12,6 +12,8 @@
#include "qts/sequencer_auto_ac_init.h"
#include "qts/sequencer_auto_inst_init.h"
+#include "qts/sequencer_auto.h"
+#include "qts/sequencer_defines.h"
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
@@ -182,6 +184,71 @@ static const struct socfpga_sdram_config sdram_config = {
.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
};
+static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
+ .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
+ .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ .activate_1 = RW_MGR_ACTIVATE_1,
+ .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
+ .guaranteed_read = RW_MGR_GUARANTEED_READ,
+ .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
+ .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
+ .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
+ .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
+ .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
+ .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
+ .idle = RW_MGR_IDLE,
+ .idle_loop1 = RW_MGR_IDLE_LOOP1,
+ .idle_loop2 = RW_MGR_IDLE_LOOP2,
+ .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
+ .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
+ .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
+ .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
+ .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
+ .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+ .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+ .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
+ .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
+ .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
+ .mrs0_user = RW_MGR_MRS0_USER,
+ .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
+ .mrs1 = RW_MGR_MRS1,
+ .mrs1_mirr = RW_MGR_MRS1_MIRR,
+ .mrs2 = RW_MGR_MRS2,
+ .mrs2_mirr = RW_MGR_MRS2_MIRR,
+ .mrs3 = RW_MGR_MRS3,
+ .mrs3_mirr = RW_MGR_MRS3_MIRR,
+ .precharge_all = RW_MGR_PRECHARGE_ALL,
+ .read_b2b = RW_MGR_READ_B2B,
+ .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
+ .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
+ .refresh_all = RW_MGR_REFRESH_ALL,
+ .rreturn = RW_MGR_RETURN,
+ .sgle_read = RW_MGR_SGLE_READ,
+ .zqcl = RW_MGR_ZQCL,
+
+ .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
+ .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
+ .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
+ .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
+ .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
+ .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+ .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
+ .mem_virtual_groups_per_read_dqs =
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+ .mem_virtual_groups_per_write_dqs =
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
+};
+
const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
{
return &sdram_config;
@@ -198,3 +265,8 @@ void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
*init = inst_rom_init;
*nelem = ARRAY_SIZE(inst_rom_init);
}
+
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
+{
+ return &rw_mgr_config;
+}
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 31e339b..11f96a5 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -41,6 +41,8 @@ static struct socfpga_data_mgr *data_mgr =
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+const struct socfpga_sdram_rw_mgr_config *rwcfg;
+
#define DELTA_D 1
/*
@@ -3696,6 +3698,8 @@ int sdram_calibration_full(void)
param = &my_param;
gbl = &my_gbl;
+ rwcfg = socfpga_get_sdram_rwmgr_config();
+
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 07/15] ddr: altera: sequencer: Pluck out RW_MGR_* macros from code
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (5 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 06/15] ddr: altera: sequencer: Wrap RW_MGR_* macros Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:58 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 08/15] ddr: altera: sequencer: Wrap IO_* macros Marek Vasut
` (7 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed excercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 292 ++++++++++++++++++++---------------------
drivers/ddr/altera/sequencer.h | 16 +--
2 files changed, 154 insertions(+), 154 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 11f96a5..41af859 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -144,12 +144,12 @@ static void phy_mgr_initialize(void)
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
return;
- ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ ratio = rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
param->read_correct_mask_vg = (1 << ratio) - 1;
param->write_correct_mask_vg = (1 << ratio) - 1;
- param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
- param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+ param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1;
+ param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;
}
/**
@@ -169,14 +169,14 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
odt_mask_0 = 0x0;
odt_mask_1 = 0x0;
} else { /* RW_MGR_ODT_MODE_READ_WRITE */
- switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
+ switch (rwcfg->mem_number_of_ranks) {
case 1: /* 1 Rank */
/* Read: ODT = 0 ; Write: ODT = 1 */
odt_mask_0 = 0x0;
odt_mask_1 = 0x1;
break;
case 2: /* 2 Ranks */
- if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
+ if (rwcfg->mem_number_of_cs_per_dimm == 1) {
/*
* - Dual-Slot , Single-Rank (1 CS per DIMM)
* OR
@@ -313,7 +313,7 @@ static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
{
- scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
@@ -329,14 +329,14 @@ static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
{
- scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
- RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
+ rwcfg->mem_dq_per_write_dqs + 1 + dm,
delay);
}
@@ -379,7 +379,7 @@ static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
{
u32 r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set(off, grp, val);
@@ -444,8 +444,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
*/
static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
{
- const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
@@ -501,9 +501,9 @@ static void scc_mgr_zero_all(void)
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
/*
* The phases actually don't exist on a per-rank basis,
* but there's no harm updating them several times, so
@@ -514,7 +514,7 @@ static void scc_mgr_zero_all(void)
scc_mgr_set_dqs_en_delay(i, 0);
}
- for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
/* Arria V/Cyclone V don't have out2. */
scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
@@ -556,8 +556,8 @@ static void scc_set_bypass_mode(const u32 write_group)
*/
static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
{
- const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
@@ -580,10 +580,10 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
{
int i, r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/* Zero all DQ config settings. */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
scc_mgr_set_dq_in_delay(i, 0);
@@ -624,7 +624,7 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
{
uint32_t i, p;
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
+ for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
@@ -640,7 +640,7 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
{
int i;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
@@ -682,7 +682,7 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
u32 i, new_delay;
/* DQ shift */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)
scc_mgr_load_dq(i);
/* DM shift */
@@ -731,7 +731,7 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
{
int r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group, delay);
writel(0, &sdr_scc_mgr->update);
@@ -752,7 +752,7 @@ static void set_jump_as_return(void)
* we always jump.
*/
writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/**
@@ -807,10 +807,10 @@ static void delay_for_n_mem_clocks(const u32 clocks)
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_IDLE_LOOP1,
+ writel(rwcfg->idle_loop1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
@@ -819,14 +819,14 @@ static void delay_for_n_mem_clocks(const u32 clocks)
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_IDLE_LOOP2,
+ writel(rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_IDLE_LOOP2,
+ writel(rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
do {
- writel(RW_MGR_IDLE_LOOP2,
+ writel(rwcfg->idle_loop2,
SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
@@ -880,39 +880,39 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
u32 r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
if (precharge)
- writel(RW_MGR_PRECHARGE_ALL, grpaddr);
+ writel(rwcfg->precharge_all, grpaddr);
/*
* USER Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ if ((rwcfg->mem_address_mirroring >> r) & 0x1) {
set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, grpaddr);
+ writel(rwcfg->mrs2_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, grpaddr);
+ writel(rwcfg->mrs3_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, grpaddr);
+ writel(rwcfg->mrs1_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
writel(fin1, grpaddr);
} else {
set_jump_as_return();
- writel(RW_MGR_MRS2, grpaddr);
+ writel(rwcfg->mrs2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, grpaddr);
+ writel(rwcfg->mrs3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, grpaddr);
+ writel(rwcfg->mrs1, grpaddr);
set_jump_as_return();
writel(fin2, grpaddr);
}
@@ -921,7 +921,7 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
continue;
set_jump_as_return();
- writel(RW_MGR_ZQCL, grpaddr);
+ writel(rwcfg->zqcl, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
@@ -966,7 +966,7 @@ static void rw_mgr_mem_initialize(void)
*/
rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
SEQ_TINIT_CNTR2_VAL,
- RW_MGR_INIT_RESET_0_CKE_0);
+ rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
writel(1, &phy_mgr_cfg->reset_mem_stbl);
@@ -987,14 +987,14 @@ static void rw_mgr_mem_initialize(void)
*/
rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
SEQ_TRESET_CNTR2_VAL,
- RW_MGR_INIT_RESET_1_CKE_0);
+ rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
/* tXRP < 250 ck cycles */
delay_for_n_mem_clocks(250);
- rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
+ rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset,
0);
}
@@ -1006,7 +1006,7 @@ static void rw_mgr_mem_initialize(void)
*/
static void rw_mgr_mem_handoff(void)
{
- rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
+ rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1);
/*
* Need to wait tMOD (12CK or 15ns) time before issuing other
* commands, but we will have plenty of NIOS cycles before actual
@@ -1070,16 +1070,16 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
/* CNTR 3 - Not used */
if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_data,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
+ writel(rwcfg->lfsr_wr_rd_bank_0_data,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ writel(rwcfg->lfsr_wr_rd_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
@@ -1092,12 +1092,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
/* CNTR 3 - Not used */
if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
+ writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
@@ -1115,12 +1115,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
*/
writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
+ writel(rwcfg->lfsr_wr_rd_bank_0_nop,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
@@ -1142,10 +1142,10 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ writel(rwcfg->lfsr_wr_rd_bank_0_wait,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
@@ -1171,10 +1171,10 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
u32 *bit_chk, const u32 all_ranks)
{
const u32 rank_end = all_ranks ?
- RW_MGR_MEM_NUMBER_OF_RANKS :
+ rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- const u32 shift_ratio = RW_MGR_MEM_DQ_PER_WRITE_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS;
+ const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /
+ rwcfg->mem_virtual_groups_per_write_dqs;
const u32 correct_mask_vg = param->write_correct_mask_vg;
u32 tmp_bit_chk, base_rw_mgr;
@@ -1187,14 +1187,14 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;
+ for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1;
vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
rw_mgr_mem_calibrate_write_test_issue(
write_group *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS + vg,
+ rwcfg->mem_virtual_groups_per_write_dqs + vg,
use_dm);
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
@@ -1238,12 +1238,12 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
const u32 addr_offset =
- (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
+ (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2;
const u32 rank_end = all_ranks ?
- RW_MGR_MEM_NUMBER_OF_RANKS :
+ rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
const u32 correct_mask_vg = param->read_correct_mask_vg;
u32 tmp_bit_chk, base_rw_mgr, bit_chk;
@@ -1258,21 +1258,21 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
/* Load up a constant bursts of read commands */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_GUARANTEED_READ,
+ writel(rwcfg->guaranteed_read,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_GUARANTEED_READ_CONT,
+ writel(rwcfg->guaranteed_read_cont,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
+ for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
- writel(RW_MGR_GUARANTEED_READ,
+ writel(rwcfg->guaranteed_read,
addr + addr_offset + (vg << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
@@ -1283,7 +1283,7 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
bit_chk &= tmp_bit_chk;
}
- writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
+ writel(rwcfg->clear_dqs_enable, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1309,7 +1309,7 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
const int all_ranks)
{
const u32 rank_end = all_ranks ?
- RW_MGR_MEM_NUMBER_OF_RANKS :
+ rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
u32 r;
@@ -1322,25 +1322,25 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
/* Load up a constant bursts */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ writel(rwcfg->guaranteed_write_wait0,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ writel(rwcfg->guaranteed_write_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ writel(rwcfg->guaranteed_write_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ writel(rwcfg->guaranteed_write_wait3,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
@@ -1367,7 +1367,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
u32 *bit_chk,
const u32 all_groups, const u32 all_ranks)
{
- const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
const u32 quick_read_mode =
((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
@@ -1387,11 +1387,11 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_READ_B2B_WAIT1,
+ writel(rwcfg->read_b2b_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(RW_MGR_READ_B2B_WAIT2,
+ writel(rwcfg->read_b2b_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
if (quick_read_mode)
@@ -1402,20 +1402,20 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
else
writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_READ_B2B,
+ writel(rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
+ writel(rwcfg->mem_if_read_dqs_width *
+ rwcfg->mem_virtual_groups_per_read_dqs - 1,
&sdr_rw_load_mgr_regs->load_cntr3);
else
writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(RW_MGR_READ_B2B,
+ writel(rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
+ for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
@@ -1430,13 +1430,13 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
}
- writel(RW_MGR_READ_B2B, addr +
- ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
+ writel(rwcfg->read_b2b, addr +
+ ((group * rwcfg->mem_virtual_groups_per_read_dqs +
vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
}
@@ -1444,7 +1444,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
+ writel(rwcfg->clear_dqs_enable, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1972,12 +1972,12 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn,
u32 *bit_chk, u32 *sticky_bit_chk,
const u32 use_read_test)
{
- const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const u32 ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const u32 correct_mask = write ? param->write_correct_mask :
param->read_correct_mask;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
u32 ret;
/*
* Stop searching when the read test doesn't pass AND when
@@ -2029,8 +2029,8 @@ static void search_left_edge(const int write, const int rank_bgn,
{
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
int i, d;
@@ -2140,8 +2140,8 @@ static int search_right_edge(const int write, const int rank_bgn,
{
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
int i, d;
@@ -2167,7 +2167,7 @@ static int search_right_edge(const int write, const int rank_bgn,
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
/*
* d = 0 failed, but it passed when
* testing the left edge, so it must be
@@ -2257,8 +2257,8 @@ static int search_right_edge(const int write, const int rank_bgn,
static int get_window_mid_index(const int write, int *left_edge,
int *right_edge, int *mid_min)
{
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
int i, mid, min_index;
/* Find middle of window for each DQ bit */
@@ -2307,8 +2307,8 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
int *dq_margin, int *dqs_margin)
{
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
SCC_MGR_IO_IN_DELAY_OFFSET;
const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
@@ -2387,8 +2387,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
* signed numbers.
*/
uint32_t sticky_bit_chk;
- int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
+ int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
+ int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
int32_t orig_mid_min, mid_min;
int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
int32_t dq_margin, dqs_margin;
@@ -2404,7 +2404,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
/* set the left and right edge of each bit to an illegal value */
/* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
sticky_bit_chk = 0;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
@@ -2438,12 +2438,12 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
set_failing_group_stage(rw_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO,
CAL_SUBSTAGE_VFIFO_CENTER);
} else {
set_failing_group_stage(rw_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
}
@@ -2568,17 +2568,17 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
/* We start at zero, so have one less dq to devide among */
const u32 delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ (rwcfg->mem_dq_per_read_dqs - 1);
int ret;
u32 i, p, d, r;
debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
/* Try different dq_in_delays since the DQ path is shorter than DQS. */
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0, p = test_bgn, d = 0;
- i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i < rwcfg->mem_dq_per_read_dqs;
i++, p++, d += delay_step) {
debug_cond(DLEVEL == 1,
"%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
@@ -2601,7 +2601,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
__func__, __LINE__, rw_group, !ret);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
writel(0, &sdr_scc_mgr->update);
@@ -2635,7 +2635,7 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
*/
grp_calibrated = 1;
for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn < rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
test_bgn,
@@ -2939,8 +2939,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
int i;
u32 sticky_bit_chk;
u32 min_index;
- int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
- int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
+ int left_edge[rwcfg->mem_dq_per_write_dqs];
+ int right_edge[rwcfg->mem_dq_per_write_dqs];
int mid;
int mid_min, orig_mid_min;
int new_dqs, start_dqs;
@@ -2959,7 +2959,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_IO_OUT1_DELAY_OFFSET) +
- (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ (rwcfg->mem_dq_per_write_dqs << 2));
/* Per-bit deskew. */
@@ -2968,7 +2968,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
* Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
*/
sticky_bit_chk = 0;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
}
@@ -3129,24 +3129,24 @@ static void mem_precharge_and_activate(void)
{
int r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
/* Set rank. */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* Precharge all banks. */
- writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ writel(rwcfg->activate_0_and_1_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ writel(rwcfg->activate_0_and_1_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* Activate rows. */
- writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
@@ -3203,13 +3203,13 @@ static void mem_skip_calibrate(void)
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/*
* Set output phase alignment settings appropriate for
* skip calibration.
*/
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_en_phase(i, 0);
#if IO_DLL_CHAIN_LENGTH == 6
scc_mgr_set_dqdqs_output_phase(i, 6);
@@ -3247,7 +3247,7 @@ static void mem_skip_calibrate(void)
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
}
@@ -3257,7 +3257,7 @@ static void mem_skip_calibrate(void)
}
/* Compensate for simulation model behaviour */
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
@@ -3295,8 +3295,8 @@ static uint32_t mem_calibrate(void)
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
- const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
debug("%s:%d\n", __func__, __LINE__);
@@ -3313,7 +3313,7 @@ static uint32_t mem_calibrate(void)
/* Initialize bit slips. */
mem_precharge_and_activate();
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
/* Only needed once to set all groups, pins, DQ, DQS, DM. */
@@ -3350,8 +3350,8 @@ static uint32_t mem_calibrate(void)
run_groups = ~0;
for (write_group = 0, write_test_bgn = 0; write_group
- < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
- write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
+ < rwcfg->mem_if_write_dqs_width; write_group++,
+ write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
/* Initialize the group failure */
group_failed = 0;
@@ -3372,7 +3372,7 @@ static uint32_t mem_calibrate(void)
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
continue;
@@ -3390,7 +3390,7 @@ static uint32_t mem_calibrate(void)
/* Calibrate the output side */
for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn < rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
@@ -3417,7 +3417,7 @@ static uint32_t mem_calibrate(void)
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
@@ -3674,15 +3674,15 @@ static void initialize_tracking(void)
&sdr_reg_file->delays);
/* mux delay */
- writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
- (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
+ writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) |
+ (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0),
&sdr_reg_file->trk_rw_mgr_addr);
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ writel(rwcfg->mem_if_read_dqs_width,
&sdr_reg_file->trk_read_dqs_width);
/* trefi [7:0] */
- writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
+ writel((rwcfg->refresh_all << 24) | (1000 << 0),
&sdr_reg_file->trk_rfsh);
}
@@ -3724,14 +3724,14 @@ int sdram_calibration_full(void)
debug("%s:%d\n", __func__, __LINE__);
debug_cond(DLEVEL == 1,
"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
- RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
- RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
+ rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
+ rwcfg->mem_virtual_groups_per_read_dqs,
+ rwcfg->mem_virtual_groups_per_write_dqs);
debug_cond(DLEVEL == 1,
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
- RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
+ rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
+ rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index f621e14..3f6f7b6 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -7,14 +7,14 @@
#ifndef _SEQUENCER_H_
#define _SEQUENCER_H_
-#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-
-#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
-#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \
+ / rwcfg->mem_if_write_dqs_width)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \
+ / rwcfg->mem_if_write_dqs_width)
+
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \
+ / rwcfg->mem_if_write_dqs_width)
+#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 08/15] ddr: altera: sequencer: Wrap IO_* macros
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (6 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 07/15] ddr: altera: sequencer: Pluck out RW_MGR_* macros from code Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 15:59 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 09/15] ddr: altera: sequencer: Pluck out IO_* macros from code Marek Vasut
` (6 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the polution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 19 +++++++++++++++++++
board/altera/socfpga/wrap_sdram_config.c | 23 +++++++++++++++++++++++
drivers/ddr/altera/sequencer.c | 2 ++
3 files changed, 44 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index eb40934..9d0e083 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -17,6 +17,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@@ -180,6 +181,24 @@ struct socfpga_sdram_rw_mgr_config {
u8 mem_virtual_groups_per_write_dqs;
};
+struct socfpga_sdram_io_config {
+ u16 delay_per_opa_tap;
+ u8 delay_per_dchain_tap;
+ u8 delay_per_dqs_en_dchain_tap;
+ u8 dll_chain_length;
+ u8 dqdqs_out_phase_max;
+ u8 dqs_en_delay_max;
+ u8 dqs_en_delay_offset;
+ u8 dqs_en_phase_max;
+ u8 dqs_in_delay_max;
+ u8 dqs_in_reserve;
+ u8 dqs_out_reserve;
+ u8 io_in_delay_max;
+ u8 io_out1_delay_max;
+ u8 io_out2_delay_max;
+ u8 shift_dqs_en_when_shift_dqs;
+};
+
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c
index 5fe1571..2697867 100644
--- a/board/altera/socfpga/wrap_sdram_config.c
+++ b/board/altera/socfpga/wrap_sdram_config.c
@@ -249,6 +249,24 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
};
+struct socfpga_sdram_io_config io_config = {
+ .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
+ .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+ .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
+ .dll_chain_length = IO_DLL_CHAIN_LENGTH,
+ .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
+ .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
+ .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
+ .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
+ .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
+ .dqs_in_reserve = IO_DQS_IN_RESERVE,
+ .dqs_out_reserve = IO_DQS_OUT_RESERVE,
+ .io_in_delay_max = IO_IO_IN_DELAY_MAX,
+ .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
+ .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
+ .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
+};
+
const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
{
return &sdram_config;
@@ -270,3 +288,8 @@ const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
{
return &rw_mgr_config;
}
+
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
+{
+ return &io_config;
+}
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 41af859..754eaa8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -42,6 +42,7 @@ static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
const struct socfpga_sdram_rw_mgr_config *rwcfg;
+const struct socfpga_sdram_io_config *iocfg;
#define DELTA_D 1
@@ -3699,6 +3700,7 @@ int sdram_calibration_full(void)
gbl = &my_gbl;
rwcfg = socfpga_get_sdram_rwmgr_config();
+ iocfg = socfpga_get_sdram_io_config();
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 09/15] ddr: altera: sequencer: Pluck out IO_* macros from code
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (7 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 08/15] ddr: altera: sequencer: Wrap IO_* macros Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 16:00 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 10/15] ddr: altera: sequencer: Wrap misc remaining macros Marek Vasut
` (5 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 201 ++++++++++++++++++++---------------------
1 file changed, 100 insertions(+), 101 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 754eaa8..4596f55 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -510,7 +510,7 @@ static void scc_mgr_zero_all(void)
* but there's no harm updating them several times, so
* let's keep the code simple.
*/
- scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
+ scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve);
scc_mgr_set_dqs_en_phase(i, 0);
scc_mgr_set_dqs_en_delay(i, 0);
}
@@ -518,7 +518,7 @@ static void scc_mgr_zero_all(void)
for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve);
}
}
@@ -605,8 +605,8 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
scc_mgr_set_dqs_io_in_delay(0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
- scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve);
+ scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve);
scc_mgr_load_dqs_for_write_group(write_group);
/* Multicast to all DQS IO enables (only 1 in total). */
@@ -692,13 +692,13 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
/* DQS shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ if (new_delay > iocfg->io_out2_delay_max) {
debug_cond(DLEVEL == 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX,
- new_delay - IO_IO_OUT2_DELAY_MAX);
- new_delay -= IO_IO_OUT2_DELAY_MAX;
+ iocfg->io_out2_delay_max,
+ new_delay - iocfg->io_out2_delay_max);
+ new_delay -= iocfg->io_out2_delay_max;
scc_mgr_set_dqs_out1_delay(new_delay);
}
@@ -706,13 +706,13 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
/* OCT shift */
new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ if (new_delay > iocfg->io_out2_delay_max) {
debug_cond(DLEVEL == 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay,
- new_delay, IO_IO_OUT2_DELAY_MAX,
- new_delay - IO_IO_OUT2_DELAY_MAX);
- new_delay -= IO_IO_OUT2_DELAY_MAX;
+ new_delay, iocfg->io_out2_delay_max,
+ new_delay - iocfg->io_out2_delay_max);
+ new_delay -= iocfg->io_out2_delay_max;
scc_mgr_set_oct_out1_delay(write_group, new_delay);
}
@@ -1555,7 +1555,7 @@ static int find_vfifo_failing_read(const u32 grp)
static int sdr_find_phase_delay(int working, int delay, const u32 grp,
u32 *work, const u32 work_inc, u32 *pd)
{
- const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
+ const u32 max = delay ? iocfg->dqs_en_delay_max : iocfg->dqs_en_phase_max;
u32 ret;
for (; *pd <= max; (*pd)++) {
@@ -1599,11 +1599,11 @@ static int sdr_find_phase(int working, const u32 grp, u32 *work,
*p = 0;
ret = sdr_find_phase_delay(working, 0, grp, work,
- IO_DELAY_PER_OPA_TAP, p);
+ iocfg->delay_per_opa_tap, p);
if (!ret)
return 0;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ if (*p > iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
rw_mgr_incr_vfifo(grp);
if (!working)
@@ -1627,8 +1627,8 @@ static int sdr_find_phase(int working, const u32 grp, u32 *work,
static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
u32 *p, u32 *i)
{
- const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap /
+ iocfg->delay_per_dqs_en_dchain_tap;
int ret;
*work_bgn = 0;
@@ -1639,7 +1639,7 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
ret = sdr_find_phase(1, grp, work_bgn, i, p);
if (!ret)
return 0;
- *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ *work_bgn += iocfg->delay_per_dqs_en_dchain_tap;
}
/* Cannot find working solution */
@@ -1663,15 +1663,15 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
/* Special case code for backing up a phase */
if (*p == 0) {
- *p = IO_DQS_EN_PHASE_MAX;
+ *p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
} else {
(*p)--;
}
- tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
+ tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
+ for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) {
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1681,12 +1681,12 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
break;
}
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ tmp_delay += iocfg->delay_per_dqs_en_dchain_tap;
}
/* Restore VFIFO to old state before we decremented it (if needed). */
(*p)++;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ if (*p > iocfg->dqs_en_phase_max) {
*p = 0;
rw_mgr_incr_vfifo(grp);
}
@@ -1708,8 +1708,8 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
int ret;
(*p)++;
- *work_end += IO_DELAY_PER_OPA_TAP;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ *work_end += iocfg->delay_per_opa_tap;
+ if (*p > iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
*p = 0;
rw_mgr_incr_vfifo(grp);
@@ -1745,23 +1745,23 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
+ tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
- tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
- if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
- tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
- p = tmp_delay / IO_DELAY_PER_OPA_TAP;
+ tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
+ if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
+ tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
+ p = tmp_delay / iocfg->delay_per_opa_tap;
debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
- d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
- if (d > IO_DQS_EN_DELAY_MAX)
- d = IO_DQS_EN_DELAY_MAX;
- tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ d = DIV_ROUND_UP(work_mid - tmp_delay, iocfg->delay_per_dqs_en_dchain_tap);
+ if (d > iocfg->dqs_en_delay_max)
+ d = iocfg->dqs_en_delay_max;
+ tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
@@ -1814,7 +1814,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ dtaps_per_ptap = iocfg->delay_per_opa_tap / iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
find_vfifo_failing_read(grp);
@@ -1851,13 +1851,13 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/* Special case code for backing up a phase */
if (p == 0) {
- p = IO_DQS_EN_PHASE_MAX;
+ p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
} else {
p = p - 1;
}
- work_end -= IO_DELAY_PER_OPA_TAP;
+ work_end -= iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
d = 0;
@@ -1868,11 +1868,11 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/* The dtap increment to find the failing edge is done here. */
sdr_find_phase_delay(0, 1, grp, &work_end,
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
+ iocfg->delay_per_dqs_en_dchain_tap, &d);
/* Go back to working dtap */
if (d != 0)
- work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ work_end -= iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL == 2,
"%s:%d p/d: ptap=%u dtap=%u end=%u\n",
@@ -1898,7 +1898,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/* Special case code for backing up a phase */
if (p == 0) {
- p = IO_DQS_EN_PHASE_MAX;
+ p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
__func__, __LINE__, p);
@@ -1939,7 +1939,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/*
* The dynamically calculated dtaps_per_ptap is only valid if we
* found a passing/failing read. If we didn't, it means d hit the max
- * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
+ * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
* statically calculated value.
*/
if (found_passing_read && found_failing_read)
@@ -2028,8 +2028,8 @@ static void search_left_edge(const int write, const int rank_bgn,
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
- const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
@@ -2139,8 +2139,8 @@ static int search_right_edge(const int write, const int rank_bgn,
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
- const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
@@ -2152,10 +2152,10 @@ static int search_right_edge(const int write, const int rank_bgn,
d + start_dqs);
} else { /* READ-ONLY */
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
uint32_t delay = d + start_dqs_en;
- if (delay > IO_DQS_EN_DELAY_MAX)
- delay = IO_DQS_EN_DELAY_MAX;
+ if (delay > iocfg->dqs_en_delay_max)
+ delay = iocfg->dqs_en_delay_max;
scc_mgr_set_dqs_en_delay(read_group, delay);
}
scc_mgr_load_dqs(read_group);
@@ -2307,7 +2307,7 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
const int min_index, const int test_bgn,
int *dq_margin, int *dqs_margin)
{
- const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
@@ -2391,7 +2391,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
int32_t orig_mid_min, mid_min;
- int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
+ int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
int32_t dq_margin, dqs_margin;
int i, min_index;
int ret;
@@ -2399,15 +2399,15 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
start_dqs = readl(addr);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
+ if (iocfg->shift_dqs_en_when_shift_dqs)
+ start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset);
/* set the left and right edge of each bit to an illegal value */
- /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
+ /* use (iocfg->io_in_delay_max + 1) as an illegal value */
sticky_bit_chk = 0;
for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
- left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
- right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
+ left_edge[i] = iocfg->io_in_delay_max + 1;
+ right_edge[i] = iocfg->io_in_delay_max + 1;
}
/* Search for the left edge of the window for each bit */
@@ -2428,7 +2428,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
* dqs/ck relationships.
*/
scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
+ if (iocfg->shift_dqs_en_when_shift_dqs)
scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
scc_mgr_load_dqs(rw_group);
@@ -2456,8 +2456,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
/* Determine the amount we can change DQS (which is -mid_min) */
orig_mid_min = mid_min;
new_dqs = start_dqs - mid_min;
- if (new_dqs > IO_DQS_IN_DELAY_MAX)
- new_dqs = IO_DQS_IN_DELAY_MAX;
+ if (new_dqs > iocfg->dqs_in_delay_max)
+ new_dqs = iocfg->dqs_in_delay_max;
else if (new_dqs < 0)
new_dqs = 0;
@@ -2465,9 +2465,9 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
mid_min, new_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
- mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
+ if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
+ mid_min += start_dqs_en - mid_min - iocfg->dqs_en_delay_max;
else if (start_dqs_en - mid_min < 0)
mid_min += start_dqs_en - mid_min;
}
@@ -2476,7 +2476,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
debug_cond(DLEVEL == 1,
"vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
start_dqs,
- IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
+ iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
new_dqs, mid_min);
/* Add delay to bring centre of all DQ windows to the same "level". */
@@ -2484,7 +2484,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
min_index, test_bgn, &dq_margin, &dqs_margin);
/* Move DQS-en */
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
final_dqs_en = start_dqs_en - mid_min;
scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
scc_mgr_load_dqs(rw_group);
@@ -2568,7 +2568,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
*/
/* We start at zero, so have one less dq to devide among */
- const u32 delay_step = IO_IO_IN_DELAY_MAX /
+ const u32 delay_step = iocfg->io_in_delay_max /
(rwcfg->mem_dq_per_read_dqs - 1);
int ret;
u32 i, p, d, r;
@@ -2687,8 +2687,8 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
/* USER Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
+ dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap,
+ iocfg->delay_per_dqs_en_dchain_tap) - 1;
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
@@ -2702,7 +2702,7 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
rw_group, d);
}
- for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
+ for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) {
/* 1) Guaranteed Write */
ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
if (ret)
@@ -2861,7 +2861,7 @@ static void search_window(const int search_dm,
int *end_best, int *win_best, int new_dqs)
{
u32 bit_chk;
- const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
+ const int max = iocfg->io_out1_delay_max - new_dqs;
int d, di;
/* Search for the/part of the window with DM/DQS shift. */
@@ -2892,7 +2892,7 @@ static void search_window(const int search_dm,
* If a starting edge of our window has not been seen
* this is our current start of the DM window.
*/
- if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
+ if (*bgn_curr == iocfg->io_out1_delay_max + 1)
*bgn_curr = search_dm ? -d : d;
/*
@@ -2906,8 +2906,8 @@ static void search_window(const int search_dm,
}
} else {
/* We just saw a failing test. Reset temp edge. */
- *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ *bgn_curr = iocfg->io_out1_delay_max + 1;
+ *end_curr = iocfg->io_out1_delay_max + 1;
/* Early exit is only applicable to DQS. */
if (search_dm)
@@ -2918,7 +2918,7 @@ static void search_window(const int search_dm,
* chain space is less than already seen largest
* window we can exit.
*/
- if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
+ if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d)
break;
}
}
@@ -2946,10 +2946,10 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
int mid_min, orig_mid_min;
int new_dqs, start_dqs;
int dq_margin, dqs_margin, dm_margin;
- int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
- int end_best = IO_IO_OUT1_DELAY_MAX + 1;
+ int bgn_curr = iocfg->io_out1_delay_max + 1;
+ int end_curr = iocfg->io_out1_delay_max + 1;
+ int bgn_best = iocfg->io_out1_delay_max + 1;
+ int end_best = iocfg->io_out1_delay_max + 1;
int win_best = 0;
int ret;
@@ -2966,12 +2966,12 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
/*
* Set the left and right edge of each bit to an illegal value.
- * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
+ * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
*/
sticky_bit_chk = 0;
for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
- left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
- right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
+ left_edge[i] = iocfg->io_out1_delay_max + 1;
+ right_edge[i] = iocfg->io_out1_delay_max + 1;
}
/* Search for the left edge of the window for each bit. */
@@ -3013,10 +3013,10 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
/*
* Set the left and right edge of each bit to an illegal value.
- * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
+ * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
*/
- left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
- right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
+ left_edge[0] = iocfg->io_out1_delay_max + 1;
+ right_edge[0] = iocfg->io_out1_delay_max + 1;
/* Search for the/part of the window with DM shift. */
search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
@@ -3031,8 +3031,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
* search begins as a new search.
*/
if (end_curr != 0) {
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ bgn_curr = iocfg->io_out1_delay_max + 1;
+ end_curr = iocfg->io_out1_delay_max + 1;
}
/* Search for the/part of the window with DQS shifts. */
@@ -3212,11 +3212,10 @@ static void mem_skip_calibrate(void)
*/
for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_en_phase(i, 0);
-#if IO_DLL_CHAIN_LENGTH == 6
- scc_mgr_set_dqdqs_output_phase(i, 6);
-#else
- scc_mgr_set_dqdqs_output_phase(i, 7);
-#endif
+ if (iocfg->dll_chain_length == 6)
+ scc_mgr_set_dqdqs_output_phase(i, 6);
+ else
+ scc_mgr_set_dqdqs_output_phase(i, 7);
/*
* Case:33398
*
@@ -3235,15 +3234,15 @@ static void mem_skip_calibrate(void)
*
* Hence, to make DQS aligned to CK, we need to delay
* DQS by:
- * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
+ * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length))
*
- * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
+ * Dividing the above by (360 / iocfg->dll_chain_length)
* gives us the number of ptaps, which simplies to:
*
- * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
+ * (1.25 * iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- 1.25 * IO_DLL_CHAIN_LENGTH - 2);
+ 1.25 * iocfg->dll_chain_length - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
@@ -3656,7 +3655,7 @@ static void initialize_tracking(void)
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
+ writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
/* trk_sample_count */
@@ -3734,17 +3733,17 @@ int sdram_calibration_full(void)
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
- IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
+ iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
+ iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
- IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
- IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
+ iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
+ iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
- IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
- IO_IO_OUT2_DELAY_MAX);
+ iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
+ iocfg->io_out2_delay_max);
debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
- IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
+ iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
hc_initialize_rom_data();
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 10/15] ddr: altera: sequencer: Wrap misc remaining macros
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (8 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 09/15] ddr: altera: sequencer: Pluck out IO_* macros from code Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 16:02 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 11/15] ddr: altera: sequencer: Zap VFIFO_SIZE Marek Vasut
` (4 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Introduce structure socfpga_sdram_misc_config to wrap the remainging
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the polution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 17 +++++++++++++++++
board/altera/socfpga/wrap_sdram_config.c | 21 +++++++++++++++++++++
drivers/ddr/altera/sequencer.c | 2 ++
3 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 9d0e083..f12bb84 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -18,6 +18,7 @@ void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@@ -199,6 +200,22 @@ struct socfpga_sdram_io_config {
u8 shift_dqs_en_when_shift_dqs;
};
+struct socfpga_sdram_misc_config {
+ u32 reg_file_init_seq_signature;
+ u8 afi_rate_ratio;
+ u8 calib_lfifo_offset;
+ u8 calib_vfifo_offset;
+ u8 enable_super_quick_calibration;
+ u8 max_latency_count_width;
+ u8 read_valid_fifo_size;
+ u8 tinit_cntr0_val;
+ u8 tinit_cntr1_val;
+ u8 tinit_cntr2_val;
+ u8 treset_cntr0_val;
+ u8 treset_cntr1_val;
+ u8 treset_cntr2_val;
+};
+
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
diff --git a/board/altera/socfpga/wrap_sdram_config.c b/board/altera/socfpga/wrap_sdram_config.c
index 2697867..cd97cc5 100644
--- a/board/altera/socfpga/wrap_sdram_config.c
+++ b/board/altera/socfpga/wrap_sdram_config.c
@@ -267,6 +267,22 @@ struct socfpga_sdram_io_config io_config = {
.shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
};
+struct socfpga_sdram_misc_config misc_config = {
+ .afi_rate_ratio = AFI_RATE_RATIO,
+ .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
+ .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
+ .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
+ .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
+ .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
+ .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
+ .tinit_cntr0_val = TINIT_CNTR0_VAL,
+ .tinit_cntr1_val = TINIT_CNTR1_VAL,
+ .tinit_cntr2_val = TINIT_CNTR2_VAL,
+ .treset_cntr0_val = TRESET_CNTR0_VAL,
+ .treset_cntr1_val = TRESET_CNTR1_VAL,
+ .treset_cntr2_val = TRESET_CNTR2_VAL,
+};
+
const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
{
return &sdram_config;
@@ -293,3 +309,8 @@ const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
{
return &io_config;
}
+
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
+{
+ return &misc_config;
+}
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4596f55..70956fa 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -43,6 +43,7 @@ static struct socfpga_sdr_ctrl *sdr_ctrl =
const struct socfpga_sdram_rw_mgr_config *rwcfg;
const struct socfpga_sdram_io_config *iocfg;
+const struct socfpga_sdram_misc_config *misccfg;
#define DELTA_D 1
@@ -3700,6 +3701,7 @@ int sdram_calibration_full(void)
rwcfg = socfpga_get_sdram_rwmgr_config();
iocfg = socfpga_get_sdram_io_config();
+ misccfg = socfpga_get_sdram_misc_config();
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 11/15] ddr: altera: sequencer: Zap VFIFO_SIZE
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (9 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 10/15] ddr: altera: sequencer: Wrap misc remaining macros Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 16:03 ` Dinh Nguyen
2015-08-02 23:21 ` [U-Boot] [PATCH 12/15] ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL Marek Vasut
` (3 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 8 ++++----
drivers/ddr/altera/sequencer.h | 3 ---
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 70956fa..dd72566 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1507,7 +1507,7 @@ static void rw_mgr_decr_vfifo(const u32 grp)
{
u32 i;
- for (i = 0; i < VFIFO_SIZE - 1; i++)
+ for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
rw_mgr_incr_vfifo(grp);
}
@@ -1521,7 +1521,7 @@ static int find_vfifo_failing_read(const u32 grp)
{
u32 v, ret, fail_cnt = 0;
- for (v = 0; v < VFIFO_SIZE; v++) {
+ for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1592,7 +1592,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
- const u32 end = VFIFO_SIZE + (working ? 0 : 1);
+ const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
int ret;
for (; *i < end; (*i)++) {
@@ -1773,7 +1773,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
- for (i = 0; i < VFIFO_SIZE; i++) {
+ for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 3f6f7b6..a80f227 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -65,9 +65,6 @@
#define CAL_SUBSTAGE_READ_LATENCY 1
#define CAL_SUBSTAGE_REFRESH 1
-/* length of VFIFO, from SW_MACROS */
-#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
-
#define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
#define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
#define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 12/15] ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (10 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 11/15] ddr: altera: sequencer: Zap VFIFO_SIZE Marek Vasut
@ 2015-08-02 23:21 ` Marek Vasut
2015-08-03 16:04 ` Dinh Nguyen
2015-08-02 23:22 ` [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code Marek Vasut
` (2 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:21 UTC (permalink / raw)
To: u-boot
This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 8 ++++----
drivers/ddr/altera/sequencer.h | 45 ------------------------------------------
2 files changed, 4 insertions(+), 49 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index dd72566..f6414e0 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -966,8 +966,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
- SEQ_TINIT_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+ TINIT_CNTR2_VAL,
rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
@@ -987,8 +987,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
- SEQ_TRESET_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+ TRESET_CNTR2_VAL,
rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index a80f227..839a374 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -122,51 +122,6 @@
#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
-/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
- * otherwise, revert to defaults
- * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
- * 200.75us @ 266MHz
- */
-#ifdef TINIT_CNTR0_VAL
-#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
-#else
-#define SEQ_TINIT_CNTR0_VAL 0
-#endif
-
-#ifdef TINIT_CNTR1_VAL
-#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
-#else
-#define SEQ_TINIT_CNTR1_VAL 202
-#endif
-
-#ifdef TINIT_CNTR2_VAL
-#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
-#else
-#define SEQ_TINIT_CNTR2_VAL 131
-#endif
-
-
-/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
- * 500.86us @ 266MHz
- */
-#ifdef TRESET_CNTR0_VAL
-#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
-#else
-#define SEQ_TRESET_CNTR0_VAL 2
-#endif
-
-#ifdef TRESET_CNTR1_VAL
-#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
-#else
-#define SEQ_TRESET_CNTR1_VAL 252
-#endif
-
-#ifdef TRESET_CNTR2_VAL
-#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
-#else
-#define SEQ_TRESET_CNTR2_VAL 131
-#endif
-
struct socfpga_sdr_rw_load_manager {
u32 load_cntr0;
u32 load_cntr1;
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (11 preceding siblings ...)
2015-08-02 23:21 ` [U-Boot] [PATCH 12/15] ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL Marek Vasut
@ 2015-08-02 23:22 ` Marek Vasut
2015-08-03 16:06 ` Dinh Nguyen
2015-08-02 23:22 ` [U-Boot] [PATCH 14/15] ddr: altera: sequencer: Clean data types Marek Vasut
2015-08-02 23:22 ` [U-Boot] [PATCH 15/15] ddr: altera: sequencer: Clean checkpatch issues Marek Vasut
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:22 UTC (permalink / raw)
To: u-boot
Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed excercise here, no
manual coding needed.
This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 37 +++++++++++++++----------------------
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f6414e0..e6cc12e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -10,13 +10,6 @@
#include <errno.h>
#include "sequencer.h"
-/*
- * FIXME: This path is temporary until the SDRAM driver gets
- * a proper thorough cleanup.
- */
-#include "../../../board/altera/socfpga/qts/sequencer_auto.h"
-#include "../../../board/altera/socfpga/qts/sequencer_defines.h"
-
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
@@ -773,7 +766,7 @@ static void delay_for_n_mem_clocks(const u32 clocks)
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
/* Scale (rounding up) to get afi clocks. */
- afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
+ afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio);
if (afi_clocks) /* Temporary underflow protection */
afi_clocks--;
@@ -966,8 +959,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
- TINIT_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, misccfg->tinit_cntr1_val,
+ misccfg->tinit_cntr2_val,
rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
@@ -987,8 +980,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
- TRESET_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, misccfg->treset_cntr1_val,
+ misccfg->treset_cntr2_val,
rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
@@ -1029,7 +1022,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
{
const u32 quick_write_mode =
(STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
- ENABLE_SUPER_QUICK_CALIBRATION;
+ misccfg->enable_super_quick_calibration;
u32 mcc_instruction;
u32 rw_wl_nop_cycles;
@@ -1373,7 +1366,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
const u32 quick_read_mode =
((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
- ENABLE_SUPER_QUICK_CALIBRATION);
+ misccfg->enable_super_quick_calibration);
u32 correct_mask_vg = param->read_correct_mask_vg;
u32 tmp_bit_chk;
u32 base_rw_mgr;
@@ -1507,7 +1500,7 @@ static void rw_mgr_decr_vfifo(const u32 grp)
{
u32 i;
- for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
+ for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++)
rw_mgr_incr_vfifo(grp);
}
@@ -1521,7 +1514,7 @@ static int find_vfifo_failing_read(const u32 grp)
{
u32 v, ret, fail_cnt = 0;
- for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
+ for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1592,7 +1585,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
- const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
+ const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1);
int ret;
for (; *i < end; (*i)++) {
@@ -1773,7 +1766,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
- for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
+ for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
@@ -3165,7 +3158,7 @@ static void mem_init_latency(void)
* so max latency in AFI clocks, used here, is correspondingly
* smaller.
*/
- const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
+ const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1;
u32 rlat, wlat;
debug("%s:%d\n", __func__, __LINE__);
@@ -3268,7 +3261,7 @@ static void mem_skip_calibrate(void)
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
- vfifo_offset = CALIB_VFIFO_OFFSET;
+ vfifo_offset = misccfg->calib_vfifo_offset;
for (j = 0; j < vfifo_offset; j++)
writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
writel(0, &phy_mgr_cmd->fifo_reset);
@@ -3277,7 +3270,7 @@ static void mem_skip_calibrate(void)
* For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
* setting from generation-time constant.
*/
- gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
+ gbl->curr_read_lat = misccfg->calib_lfifo_offset;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
@@ -3585,7 +3578,7 @@ static void hc_initialize_rom_data(void)
static void initialize_reg_file(void)
{
/* Initialize the register file with the correct data */
- writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
+ writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature);
writel(0, &sdr_reg_file->debug_data_addr);
writel(0, &sdr_reg_file->cur_stage);
writel(0, &sdr_reg_file->fom);
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code
2015-08-02 23:22 ` [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code Marek Vasut
@ 2015-08-03 16:06 ` Dinh Nguyen
2015-08-03 16:23 ` Marek Vasut
0 siblings, 1 reply; 32+ messages in thread
From: Dinh Nguyen @ 2015-08-03 16:06 UTC (permalink / raw)
To: u-boot
On 08/02/2015 06:22 PM, Marek Vasut wrote:
> Actually convert the sequencer code to use socfpga_sdram_misc_config
> instead of the various macros. This is just an sed excercise here, no
> manual coding needed.
>
> This patch actually removes the need to include any board-specific
> files in sequencer.c , so sequencer.c namespace is now no longer
> poluted by QTS-generated macros.
>
s/excercise/exercise
s/poluted/polluted
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Thanks,
Dinh
^ permalink raw reply [flat|nested] 32+ messages in thread
* [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code
2015-08-03 16:06 ` Dinh Nguyen
@ 2015-08-03 16:23 ` Marek Vasut
0 siblings, 0 replies; 32+ messages in thread
From: Marek Vasut @ 2015-08-03 16:23 UTC (permalink / raw)
To: u-boot
On Monday, August 03, 2015 at 06:06:25 PM, Dinh Nguyen wrote:
> On 08/02/2015 06:22 PM, Marek Vasut wrote:
> > Actually convert the sequencer code to use socfpga_sdram_misc_config
> > instead of the various macros. This is just an sed excercise here, no
> > manual coding needed.
> >
> > This patch actually removes the need to include any board-specific
> > files in sequencer.c , so sequencer.c namespace is now no longer
> > poluted by QTS-generated macros.
>
> s/excercise/exercise
> s/poluted/polluted
>
> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Broken english fixed, thanks!
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 32+ messages in thread
* [U-Boot] [PATCH 14/15] ddr: altera: sequencer: Clean data types
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (12 preceding siblings ...)
2015-08-02 23:22 ` [U-Boot] [PATCH 13/15] ddr: altera: sequencer: Pluck out misc macros from code Marek Vasut
@ 2015-08-02 23:22 ` Marek Vasut
2015-08-03 16:06 ` Dinh Nguyen
2015-08-02 23:22 ` [U-Boot] [PATCH 15/15] ddr: altera: sequencer: Clean checkpatch issues Marek Vasut
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:22 UTC (permalink / raw)
To: u-boot
Replace uintNN_t with uNN. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 96 +++++++++++++++++++++---------------------
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e6cc12e..f2d164a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -60,7 +60,7 @@ const struct socfpga_sdram_misc_config *misccfg;
STATIC_SKIP_DELAY_LOOPS)
/* calibration steps requested by the rtl */
-uint16_t dyn_calib_steps;
+u16 dyn_calib_steps;
/*
* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
@@ -71,7 +71,7 @@ uint16_t dyn_calib_steps;
* zero when skipping
*/
-uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
+u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
((non_skip_value) & skip_delay_mask)
@@ -79,8 +79,8 @@ uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
struct gbl_type *gbl;
struct param_type *param;
-static void set_failing_group_stage(uint32_t group, uint32_t stage,
- uint32_t substage)
+static void set_failing_group_stage(u32 group, u32 stage,
+ u32 substage)
{
/*
* Only set the global stage if there was not been any other
@@ -286,49 +286,49 @@ static void scc_mgr_initialize(void)
}
}
-static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
+static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
{
scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
}
-static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
{
scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
{
scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
}
-static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
{
scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
+static void scc_mgr_set_dqs_io_in_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
-static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
+static void scc_mgr_set_dqs_out1_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
-static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
+static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
rwcfg->mem_dq_per_write_dqs + 1 + dm,
@@ -336,7 +336,7 @@ static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
}
/* load up dqs config settings */
-static void scc_mgr_load_dqs(uint32_t dqs)
+static void scc_mgr_load_dqs(u32 dqs)
{
writel(dqs, &sdr_scc_mgr->dqs_ena);
}
@@ -348,13 +348,13 @@ static void scc_mgr_load_dqs_io(void)
}
/* load up dq config settings */
-static void scc_mgr_load_dq(uint32_t dq_in_group)
+static void scc_mgr_load_dq(u32 dq_in_group)
{
writel(dq_in_group, &sdr_scc_mgr->dq_ena);
}
/* load up dm config settings */
-static void scc_mgr_load_dm(uint32_t dm)
+static void scc_mgr_load_dm(u32 dm)
{
writel(dm, &sdr_scc_mgr->dm_ena);
}
@@ -399,8 +399,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
read_group, phase, 0);
}
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
- uint32_t phase)
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
+ u32 phase)
{
/*
* USER although the h/w doesn't support different phases per
@@ -414,8 +414,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
write_group, phase, 0);
}
-static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
+ u32 delay)
{
/*
* In shadow register mode, the T11 settings are stored in
@@ -615,9 +615,9 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
+static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
{
- uint32_t i, p;
+ u32 i, p;
for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
scc_mgr_set_dq_in_delay(p, delay);
@@ -642,9 +642,9 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
{
- uint32_t i;
+ u32 i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
scc_mgr_set_dm_out1_delay(i, delay1);
@@ -654,8 +654,8 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
/* apply and load delay on both DQS and OCT out1 */
-static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
+ u32 delay)
{
scc_mgr_set_dqs_out1_delay(delay);
scc_mgr_load_dqs_io();
@@ -840,7 +840,7 @@ static void delay_for_n_mem_clocks(const u32 clocks)
*/
static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
{
- uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
/* Load counters */
@@ -2147,7 +2147,7 @@ static int search_right_edge(const int write, const int rank_bgn,
} else { /* READ-ONLY */
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
if (iocfg->shift_dqs_en_when_shift_dqs) {
- uint32_t delay = d + start_dqs_en;
+ u32 delay = d + start_dqs_en;
if (delay > iocfg->dqs_en_delay_max)
delay = iocfg->dqs_en_delay_max;
scc_mgr_set_dqs_en_delay(read_group, delay);
@@ -2381,7 +2381,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
* Store these as signed since there are comparisons with
* signed numbers.
*/
- uint32_t sticky_bit_chk;
+ u32 sticky_bit_chk;
int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
int32_t orig_mid_min, mid_min;
@@ -2665,9 +2665,9 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
*/
static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
- uint32_t p, d;
- uint32_t dtaps_per_ptap;
- uint32_t failed_substage;
+ u32 p, d;
+ u32 dtaps_per_ptap;
+ u32 failed_substage;
int ret;
@@ -2783,7 +2783,7 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
* Calibrate LFIFO to find smallest read latency.
*/
-static uint32_t rw_mgr_mem_calibrate_lfifo(void)
+static u32 rw_mgr_mem_calibrate_lfifo(void)
{
int found_one = 0;
@@ -3193,8 +3193,8 @@ static void mem_init_latency(void)
*/
static void mem_skip_calibrate(void)
{
- uint32_t vfifo_offset;
- uint32_t i, j, r;
+ u32 vfifo_offset;
+ u32 i, j, r;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
@@ -3279,15 +3279,15 @@ static void mem_skip_calibrate(void)
*
* Perform memory calibration.
*/
-static uint32_t mem_calibrate(void)
+static u32 mem_calibrate(void)
{
- uint32_t i;
- uint32_t rank_bgn, sr;
- uint32_t write_group, write_test_bgn;
- uint32_t read_group, read_test_bgn;
- uint32_t run_groups, current_run;
- uint32_t failing_groups = 0;
- uint32_t group_failed = 0;
+ u32 i;
+ u32 rank_bgn, sr;
+ u32 write_group, write_test_bgn;
+ u32 read_group, read_test_bgn;
+ u32 run_groups, current_run;
+ u32 failing_groups = 0;
+ u32 group_failed = 0;
const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
rwcfg->mem_if_write_dqs_width;
@@ -3506,7 +3506,7 @@ static int run_mem_calibrate(void)
*/
static void debug_mem_calibrate(int pass)
{
- uint32_t debug_info;
+ u32 debug_info;
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
@@ -3594,13 +3594,13 @@ static void initialize_reg_file(void)
*/
static void initialize_hps_phy(void)
{
- uint32_t reg;
+ u32 reg;
/*
* Tracking also gets configured here because it's in the
* same register.
*/
- uint32_t trk_sample_count = 7500;
- uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
+ u32 trk_sample_count = 7500;
+ u32 trk_long_idle_sample_count = (10 << 16) | 100;
/*
* Format is number of outer loops in the 16 MSB, sample
* count in 16 LSB.
@@ -3684,7 +3684,7 @@ int sdram_calibration_full(void)
{
struct param_type my_param;
struct gbl_type my_gbl;
- uint32_t pass;
+ u32 pass;
memset(&my_param, 0, sizeof(my_param));
memset(&my_gbl, 0, sizeof(my_gbl));
--
2.1.4
^ permalink raw reply related [flat|nested] 32+ messages in thread* [U-Boot] [PATCH 15/15] ddr: altera: sequencer: Clean checkpatch issues
2015-08-02 23:21 [U-Boot] [PATCH 00/15] socfpga: sequencer.c cleanups Marek Vasut
` (13 preceding siblings ...)
2015-08-02 23:22 ` [U-Boot] [PATCH 14/15] ddr: altera: sequencer: Clean data types Marek Vasut
@ 2015-08-02 23:22 ` Marek Vasut
2015-08-03 16:07 ` Dinh Nguyen
14 siblings, 1 reply; 32+ messages in thread
From: Marek Vasut @ 2015-08-02 23:22 UTC (permalink / raw)
To: u-boot
Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 159 +++++++++++++++++++++++------------------
1 file changed, 88 insertions(+), 71 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f2d164a..2bd0109 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -11,26 +11,23 @@
#include "sequencer.h"
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
- (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
-
+ (struct socfpga_sdr_rw_load_manager *)
+ (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
- (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
-
+ (struct socfpga_sdr_rw_load_jump_manager *)
+ (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
static struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
-
static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
- (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
-
+ (struct socfpga_sdr_scc_mgr *)
+ (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
(struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
-
static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
- (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
-
+ (struct socfpga_phy_mgr_cfg *)
+ (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
-
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
@@ -800,30 +797,30 @@ static void delay_for_n_mem_clocks(const u32 clocks)
*/
if (afi_clocks < 0x100) {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
- &sdr_rw_load_mgr_regs->load_cntr1);
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->idle_loop1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
- &sdr_rw_load_mgr_regs->load_cntr0);
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
- &sdr_rw_load_mgr_regs->load_cntr1);
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->idle_loop2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(rwcfg->idle_loop2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
do {
writel(rwcfg->idle_loop2,
- SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
@@ -959,7 +956,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, misccfg->tinit_cntr1_val,
+ rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val,
+ misccfg->tinit_cntr1_val,
misccfg->tinit_cntr2_val,
rwcfg->init_reset_0_cke_0);
@@ -980,7 +978,8 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, misccfg->treset_cntr1_val,
+ rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val,
+ misccfg->treset_cntr1_val,
misccfg->treset_cntr2_val,
rwcfg->init_reset_1_cke_0);
@@ -1073,9 +1072,9 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
writel(rwcfg->lfsr_wr_rd_bank_0_data,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(rwcfg->lfsr_wr_rd_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
@@ -1093,7 +1092,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
@@ -1112,11 +1111,11 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
if (test_dm) {
mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
writel(rwcfg->lfsr_wr_rd_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
@@ -1138,10 +1137,10 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
if (test_dm) {
writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
writel(rwcfg->lfsr_wr_rd_bank_0_wait,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
@@ -1254,11 +1253,11 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
/* Load up a constant bursts of read commands */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->guaranteed_read,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->guaranteed_read_cont,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
@@ -1318,22 +1317,22 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->guaranteed_write_wait0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->guaranteed_write_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
writel(rwcfg->guaranteed_write_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
writel(rwcfg->guaranteed_write_wait3,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
@@ -1383,11 +1382,11 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->read_b2b_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
writel(rwcfg->read_b2b_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
if (quick_read_mode)
writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
@@ -1398,7 +1397,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->read_b2b,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(rwcfg->mem_if_read_dqs_width *
rwcfg->mem_virtual_groups_per_read_dqs - 1,
@@ -1407,7 +1406,7 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
writel(rwcfg->read_b2b,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
@@ -1426,8 +1425,9 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
}
writel(rwcfg->read_b2b, addr +
- ((group * rwcfg->mem_virtual_groups_per_read_dqs +
- vg) << 2));
+ ((group *
+ rwcfg->mem_virtual_groups_per_read_dqs +
+ vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
@@ -1549,7 +1549,8 @@ static int find_vfifo_failing_read(const u32 grp)
static int sdr_find_phase_delay(int working, int delay, const u32 grp,
u32 *work, const u32 work_inc, u32 *pd)
{
- const u32 max = delay ? iocfg->dqs_en_delay_max : iocfg->dqs_en_phase_max;
+ const u32 max = delay ? iocfg->dqs_en_delay_max :
+ iocfg->dqs_en_phase_max;
u32 ret;
for (; *pd <= max; (*pd)++) {
@@ -1665,7 +1666,8 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) {
+ for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
+ d++) {
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1752,7 +1754,8 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
- d = DIV_ROUND_UP(work_mid - tmp_delay, iocfg->delay_per_dqs_en_dchain_tap);
+ d = DIV_ROUND_UP(work_mid - tmp_delay,
+ iocfg->delay_per_dqs_en_dchain_tap);
if (d > iocfg->dqs_en_delay_max)
d = iocfg->dqs_en_delay_max;
tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
@@ -1808,7 +1811,8 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = iocfg->delay_per_opa_tap / iocfg->delay_per_dqs_en_dchain_tap;
+ dtaps_per_ptap = iocfg->delay_per_opa_tap /
+ iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
find_vfifo_failing_read(grp);
@@ -2022,8 +2026,10 @@ static void search_left_edge(const int write, const int rank_bgn,
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max :
+ iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
@@ -2108,8 +2114,6 @@ static void search_left_edge(const int write, const int rank_bgn,
*sticky_bit_chk |= 1;
}
}
-
-
}
/**
@@ -2133,8 +2137,10 @@ static int search_right_edge(const int write, const int rank_bgn,
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max :
+ iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
@@ -2162,7 +2168,8 @@ static int search_right_edge(const int write, const int rank_bgn,
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs;
+ i++) {
/*
* d = 0 failed, but it passed when
* testing the left edge, so it must be
@@ -2301,7 +2308,8 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
const int min_index, const int test_bgn,
int *dq_margin, int *dqs_margin)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
@@ -2339,9 +2347,11 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
i, shift_dq);
if (write)
- scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
+ scc_mgr_set_dq_out1_delay(i,
+ temp_dq_io_delay1 + shift_dq);
else
- scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
+ scc_mgr_set_dq_in_delay(p,
+ temp_dq_io_delay1 + shift_dq);
scc_mgr_load_dq(p);
@@ -2357,7 +2367,6 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
*dqs_margin = right_edge[i] + shift_dq - (-mid_min);
}
-
}
/**
@@ -2461,7 +2470,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
if (iocfg->shift_dqs_en_when_shift_dqs) {
if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
- mid_min += start_dqs_en - mid_min - iocfg->dqs_en_delay_max;
+ mid_min += start_dqs_en - mid_min -
+ iocfg->dqs_en_delay_max;
else if (start_dqs_en - mid_min < 0)
mid_min += start_dqs_en - mid_min;
}
@@ -2867,8 +2877,8 @@ static void search_window(const int search_dm,
/* For DQS, we go from 0...max */
d = max - di;
/*
- * Note: This only shifts DQS, so are we limiting ourselve to
- * width of DQ unnecessarily.
+ * Note: This only shifts DQS, so are we limiting
+ * ourselves to width of DQ unnecessarily.
*/
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
@@ -3134,11 +3144,11 @@ static void mem_precharge_and_activate(void)
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->activate_0_and_1_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->activate_0_and_1_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* Activate rows. */
writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
@@ -3228,7 +3238,8 @@ static void mem_skip_calibrate(void)
*
* Hence, to make DQS aligned to CK, we need to delay
* DQS by:
- * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length))
+ * (720 - 90 - 180 - 2) *
+ * (360 / iocfg->dll_chain_length)
*
* Dividing the above by (360 / iocfg->dll_chain_length)
* gives us the number of ptaps, which simplies to:
@@ -3236,7 +3247,7 @@ static void mem_skip_calibrate(void)
* (1.25 * iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- 1.25 * iocfg->dll_chain_length - 2);
+ 1.25 * iocfg->dll_chain_length - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
@@ -3346,7 +3357,6 @@ static u32 mem_calibrate(void)
for (write_group = 0, write_test_bgn = 0; write_group
< rwcfg->mem_if_write_dqs_width; write_group++,
write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
-
/* Initialize the group failure */
group_failed = 0;
@@ -3375,7 +3385,8 @@ static u32 mem_calibrate(void)
read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
/* The group failed, we're done. */
@@ -3390,16 +3401,19 @@ static u32 mem_calibrate(void)
continue;
/* Not needed in quick mode! */
- if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
+ if (STATIC_CALIB_STEPS &
+ CALIB_SKIP_DELAY_SWEEPS)
continue;
/* Calibrate WRITEs */
if (!rw_mgr_mem_calibrate_writes(rank_bgn,
- write_group, write_test_bgn))
+ write_group,
+ write_test_bgn))
continue;
group_failed = 1;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
}
@@ -3416,10 +3430,11 @@ static u32 mem_calibrate(void)
continue;
if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
- read_test_bgn))
+ read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
/* The group failed, we're done. */
@@ -3649,7 +3664,8 @@ static void initialize_tracking(void)
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap) - 1,
+ writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap,
+ iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
/* trk_sample_count */
@@ -3731,7 +3747,8 @@ int sdram_calibration_full(void)
iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
- debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
+ debug_cond(DLEVEL == 1,
+ "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
--
2.1.4
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