From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 4 Aug 2015 08:52:33 -0700 Subject: [U-Boot] [PATCH 2/3] crypto/fsl - change starting entropy delay value In-Reply-To: <1430833715-18193-3-git-send-email-alexandru.porosanu@freescale.com> References: <1430833715-18193-1-git-send-email-alexandru.porosanu@freescale.com> <1430833715-18193-3-git-send-email-alexandru.porosanu@freescale.com> Message-ID: <55C0DFC1.7080301@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/05/2015 06:48 AM, Alex Porosanu wrote: > The entropy delay (the length in system clocks of each > entropy sample) for the RNG4 block of CAAM is dependent > on the frequency of the SoC. By elaborate methods, it > has been determined that a good starting value for all > platforms integrating the CAAM IP is 3200. Using a > higher value has additional benefit of speeding up > the process of instantiating the RNG, since the entropy > delay will be increased and instantiation of the RNG > state handles will be reattempted by the driver. If the > starting value is low, for certain platforms, this can > lead to a quite lengthy process. > This patch changes the starting value of the length of > the entropy sample to 3200 system clocks. > In addition to this change, the attempted entropy delay > values are now printed on the console upon initialization > of the RNG block. > > Signed-off-by: Alex Porosanu > --- Applied to u-boot-fsl-qoriq master with minor change in subject. Thanks. York