[U-Boot] [PATCH 1/3] zynqmp: usb: Add usb dwc3 driver support for zynqmp

[U-Boot] [PATCH 1/3] zynqmp: usb: Add usb dwc3 driver support for zynqmp

[Siva Durga Prasad Paladugu]

Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
---
 arch/arm/cpu/armv8/zynqmp/Kconfig           |    3 ++
 arch/arm/include/asm/arch-zynqmp/hardware.h |    3 ++
 board/xilinx/zynqmp/zynqmp.c                |   27 +++++++++++++++++
 configs/xilinx_zynqmp_ep_defconfig          |    1 +
 include/configs/xilinx_zynqmp.h             |   41 +++++++++++++++++++++++++-
 5 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index c8fcfb6..9a19dfa 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -20,4 +20,7 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
 
+config ZYNQMP_USB
+	bool "Configure ZynqMP USB"
+
 endif
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 7640eab..8c041c0 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -27,6 +27,9 @@
 
 #define ZYNQMP_SATA_BASEADDR	0xFD0C0000
 
+#define ZYNQMP_USB0_XHCI_BASEADDR	0xFE200000
+#define ZYNQMP_USB1_XHCI_BASEADDR	0xFE300000
+
 #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
 
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 70d9c2c..d105bb4 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -12,6 +12,8 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -137,3 +139,28 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = ZYNQMP_USB0_XHCI_BASEADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+	dwc3_uboot_handle_interrupt(0);
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	return dwc3_uboot_init(&dwc3_device_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	dwc3_uboot_exit(index);
+	return 0;
+}
+#endif
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index fda44ea..efc1bbe 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -16,3 +16,4 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep"
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_ZYNQMP_USB=y
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 68853b6..927c917 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -49,7 +49,7 @@
 #define COUNTER_FREQUENCY		4000000
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x400000)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x2000000)
 
 /* Serial setup */
 #if defined(CONFIG_ZYNQMP_DCC)
@@ -108,13 +108,50 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 
+#if defined(CONFIG_ZYNQMP_USB)
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_RAM
+#define CONFIG_G_DNL_VENDOR_NUM		0x03FD
+#define CONFIG_G_DNL_PRODUCT_NUM	0x0300
+#define CONFIG_G_DNL_MANUFACTURER	"Xilinx"
+#define CONFIG_USB_CABLE_CHECK
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+#define CONFIG_THOR_RESET_OFF
+#define DFU_ALT_INFO_RAM \
+	"dfu_ram_info=" \
+	"set dfu_alt_info " \
+	"Image ram 0x200000 0x1800000\\\\;" \
+	"system.dtb ram 0x7000000 0x40000\0" \
+	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO  \
+		DFU_ALT_INFO_RAM
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"kernel_addr=0x80000\0" \
 	"fdt_addr=0x7000000\0" \
 	"fdt_high=0x10000000\0" \
 	"sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \
-		"load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0"
+		"load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \
+	DFU_ALT_INFO
 
 #define CONFIG_BOOTARGS		"setenv bootargs console=ttyPS0,${baudrate} " \
 				"earlycon=cdns,mmio,0xff000000,${baudrate}n8"
-- 
1.7.1

[U-Boot] [PATCH 2/3] usb: zynqmp: Add XHCI driver support

[Siva Durga Prasad Paladugu]

Added USB XHCI driver support for zynqmp.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
---
 drivers/usb/host/Makefile       |    1 +
 drivers/usb/host/xhci-zynqmp.c  |  113 +++++++++++++++++++++++++++++++++++++++
 include/linux/usb/xhci-zynqmp.h |   56 +++++++++++++++++++
 3 files changed, 170 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/host/xhci-zynqmp.c
 create mode 100644 include/linux/usb/xhci-zynqmp.h

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 6cc3bbd..73d6bcb 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
 obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
 obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
diff --git a/drivers/usb/host/xhci-zynqmp.c b/drivers/usb/host/xhci-zynqmp.c
new file mode 100644
index 0000000..d56bd17
--- /dev/null
+++ b/drivers/usb/host/xhci-zynqmp.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
+ *
+ * This file was resused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/arch-zynqmp/hardware.h>
+#include <linux/compat.h>
+#include <linux/usb/xhci-zynqmp.h>
+#include <linux/usb/dwc3.h>
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct zynqmp_xhci zynqmp_xhci;
+
+unsigned long ctr_addr[] = {ZYNQMP_USB0_XHCI_BASEADDR,
+			    ZYNQMP_USB1_XHCI_BASEADDR};
+
+__weak int __board_usb_init(int index, enum usb_init_type init)
+{
+	return 0;
+}
+
+void usb_phy_reset(struct dwc3 *dwc3_reg)
+{
+	/* Assert USB3 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Assert USB2 PHY reset */
+	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+
+	mdelay(200);
+
+	/* Clear USB3 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+
+	/* Clear USB2 PHY reset */
+	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+}
+
+static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
+{
+	int ret = 0;
+
+	ret = dwc3_core_init(zynqmp_xhci->dwc3_reg);
+	if (ret) {
+		debug("%s:failed to initialize core\n", __func__);
+		return ret;
+	}
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	return ret;
+}
+
+static int zynqmp_xhci_core_exit(struct zynqmp_xhci *zynqmp_xhci)
+{
+	/*
+	 * Currently zynqmp socs do not support PHY shutdown from
+	 * sw. But this support may be added in future socs.
+	 */
+	return 0;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+	struct zynqmp_xhci *ctx = &zynqmp_xhci;
+	int ret = 0;
+
+	ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
+	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
+
+	ret = board_usb_init(index, USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+	ret = zynqmp_xhci_core_init(ctx);
+	if (ret < 0) {
+		puts("Failed to initialize xhci\n");
+		return ret;
+	}
+
+	*hccr = (struct xhci_hccr *)ctx->hcd;
+	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
+				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	debug("zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n",
+	      (uint32_t)*hccr, (uint32_t)*hcor,
+	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
+
+	return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+	struct zynqmp_xhci *ctx = &zynqmp_xhci;
+
+	zynqmp_xhci_core_exit(ctx);
+}
diff --git a/include/linux/usb/xhci-zynqmp.h b/include/linux/usb/xhci-zynqmp.h
new file mode 100644
index 0000000..c384f91
--- /dev/null
+++ b/include/linux/usb/xhci-zynqmp.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
+ *
+ * This file was resused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_ZYNQMP_H_
+#define _ASM_ARCH_XHCI_ZYNQMP_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
+#define USB3_PHY_RX_POWERON		BIT(14)
+#define USB3_PHY_TX_POWERON		BIT(15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRT		BIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN		BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	BIT(17)
+
+struct zynqmp_xhci {
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+#endif /* _ASM_ARCH_XHCI_ZYNQMP_H_ */
-- 
1.7.1

[U-Boot] [PATCH 3/3] usb: zynqmp: Enable USB XHCI support

[Siva Durga Prasad Paladugu]

Enable USB XHCI support for ZynqMP

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
---
 include/configs/xilinx_zynqmp.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 927c917..e00d4ec 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -109,6 +109,14 @@
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 
 #if defined(CONFIG_ZYNQMP_USB)
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+#define CONFIG_USB_XHCI_ZYNQMP
+
 #define CONFIG_USB_DWC3
 #define CONFIG_USB_DWC3_GADGET
 
-- 
1.7.1

[U-Boot] [PATCH 1/3] zynqmp: usb: Add usb dwc3 driver support for zynqmp

[Michal Simek]

On 08/04/2015 09:33 AM, Siva Durga Prasad Paladugu wrote:
> Added usb dwc3 driver support for zynqmp
> this also supports the DFU and LTHOR to download
> the linux images on to RAM and cen be booted from
> those linux images.
> 
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
> ---
>  arch/arm/cpu/armv8/zynqmp/Kconfig           |    3 ++
>  arch/arm/include/asm/arch-zynqmp/hardware.h |    3 ++
>  board/xilinx/zynqmp/zynqmp.c                |   27 +++++++++++++++++
>  configs/xilinx_zynqmp_ep_defconfig          |    1 +
>  include/configs/xilinx_zynqmp.h             |   41 +++++++++++++++++++++++++-
>  5 files changed, 73 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
> index c8fcfb6..9a19dfa 100644
> --- a/arch/arm/cpu/armv8/zynqmp/Kconfig
> +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
> @@ -20,4 +20,7 @@ config SYS_SOC
>  config SYS_CONFIG_NAME
>  	default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
>  
> +config ZYNQMP_USB
> +	bool "Configure ZynqMP USB"
> +
>  endif
> diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
> index 7640eab..8c041c0 100644
> --- a/arch/arm/include/asm/arch-zynqmp/hardware.h
> +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
> @@ -27,6 +27,9 @@
>  
>  #define ZYNQMP_SATA_BASEADDR	0xFD0C0000
>  
> +#define ZYNQMP_USB0_XHCI_BASEADDR	0xFE200000
> +#define ZYNQMP_USB1_XHCI_BASEADDR	0xFE300000
> +
>  #define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
>  #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
>  
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index 70d9c2c..d105bb4 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -12,6 +12,8 @@
>  #include <asm/arch/hardware.h>
>  #include <asm/arch/sys_proto.h>
>  #include <asm/io.h>
> +#include <usb.h>
> +#include <dwc3-uboot.h>
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -137,3 +139,28 @@ int checkboard(void)
>  	return 0;
>  }
>  
> +#ifdef CONFIG_USB_DWC3
> +static struct dwc3_device dwc3_device_data = {
> +	.maximum_speed = USB_SPEED_HIGH,
> +	.base = ZYNQMP_USB0_XHCI_BASEADDR,
> +	.dr_mode = USB_DR_MODE_PERIPHERAL,
> +	.index = 0,
> +};
> +
> +int usb_gadget_handle_interrupts(void)
> +{
> +	dwc3_uboot_handle_interrupt(0);
> +	return 0;
> +}
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> +	return dwc3_uboot_init(&dwc3_device_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> +	dwc3_uboot_exit(index);
> +	return 0;
> +}
> +#endif
> diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
> index fda44ea..efc1bbe 100644
> --- a/configs/xilinx_zynqmp_ep_defconfig
> +++ b/configs/xilinx_zynqmp_ep_defconfig
> @@ -16,3 +16,4 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep"
>  CONFIG_CMD_TIME=y
>  CONFIG_CMD_TIMER=y
>  CONFIG_SYS_TEXT_BASE=0x8000000
> +CONFIG_ZYNQMP_USB=y
> diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
> index 68853b6..927c917 100644
> --- a/include/configs/xilinx_zynqmp.h
> +++ b/include/configs/xilinx_zynqmp.h
> @@ -49,7 +49,7 @@
>  #define COUNTER_FREQUENCY		4000000
>  
>  /* Size of malloc() pool */
> -#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x400000)
> +#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x2000000)
>  
>  /* Serial setup */
>  #if defined(CONFIG_ZYNQMP_DCC)
> @@ -108,13 +108,50 @@
>  /* Miscellaneous configurable options */
>  #define CONFIG_SYS_LOAD_ADDR		0x8000000
>  
> +#if defined(CONFIG_ZYNQMP_USB)
> +#define CONFIG_USB_DWC3
> +#define CONFIG_USB_DWC3_GADGET
> +
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_VBUS_DRAW	2
> +#define CONFIG_USBDOWNLOAD_GADGET
> +#define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
> +#define DFU_DEFAULT_POLL_TIMEOUT	300
> +#define CONFIG_DFU_FUNCTION
> +#define CONFIG_DFU_RAM
> +#define CONFIG_G_DNL_VENDOR_NUM		0x03FD
> +#define CONFIG_G_DNL_PRODUCT_NUM	0x0300
> +#define CONFIG_G_DNL_MANUFACTURER	"Xilinx"
> +#define CONFIG_USB_CABLE_CHECK
> +#define CONFIG_CMD_DFU
> +#define CONFIG_CMD_THOR_DOWNLOAD
> +#define CONFIG_THOR_FUNCTION
> +#define CONFIG_THOR_RESET_OFF
> +#define DFU_ALT_INFO_RAM \
> +	"dfu_ram_info=" \
> +	"set dfu_alt_info " \
> +	"Image ram 0x200000 0x1800000\\\\;" \
> +	"system.dtb ram 0x7000000 0x40000\0" \
> +	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
> +	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
> +
> +#define DFU_ALT_INFO  \
> +		DFU_ALT_INFO_RAM
> +#endif
> +
> +#if !defined(DFU_ALT_INFO)
> +# define DFU_ALT_INFO
> +#endif
> +
>  /* Initial environment variables */
>  #define CONFIG_EXTRA_ENV_SETTINGS \
>  	"kernel_addr=0x80000\0" \
>  	"fdt_addr=0x7000000\0" \
>  	"fdt_high=0x10000000\0" \
>  	"sdboot=mmcinfo && load mmc 0:0 $fdt_addr system.dtb && " \
> -		"load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0"
> +		"load mmc 0:0 $kernel_addr Image && booti $kernel_addr - $fdt_addr\0" \
> +	DFU_ALT_INFO
>  
>  #define CONFIG_BOOTARGS		"setenv bootargs console=ttyPS0,${baudrate} " \
>  				"earlycon=cdns,mmio,0xff000000,${baudrate}n8"
> 

Applied.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform


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[U-Boot] [PATCH 2/3] usb: zynqmp: Add XHCI driver support

[Marek Vasut]

On Tuesday, August 04, 2015 at 09:33:27 AM, Siva Durga Prasad Paladugu wrote:
> Added USB XHCI driver support for zynqmp.
> 
> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

[...]

Hi,

You'd have much more success if you actually CCed me with the patches.

> +/* Declare global data pointer */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct zynqmp_xhci zynqmp_xhci;
> +
> +unsigned long ctr_addr[] = {ZYNQMP_USB0_XHCI_BASEADDR,
> +			    ZYNQMP_USB1_XHCI_BASEADDR};

Will you always init both controllers ?

> +__weak int __board_usb_init(int index, enum usb_init_type init)
> +{
> +	return 0;
> +}
> +
> +void usb_phy_reset(struct dwc3 *dwc3_reg)
> +{
> +	/* Assert USB3 PHY reset */
> +	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> +	/* Assert USB2 PHY reset */
> +	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +
> +	mdelay(200);

Is such a lengthy delay really needed ?

> +	/* Clear USB3 PHY reset */
> +	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> +
> +	/* Clear USB2 PHY reset */
> +	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> +}

[...]

> +static int zynqmp_xhci_core_exit(struct zynqmp_xhci *zynqmp_xhci)
> +{
> +	/*
> +	 * Currently zynqmp socs do not support PHY shutdown from
> +	 * sw. But this support may be added in future socs.
> +	 */
> +	return 0;

Please wrap this into xhci_hcd_stop(), no need for this ad-hoc function.

> +}
> +
> +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor
> **hcor) +{
> +	struct zynqmp_xhci *ctx = &zynqmp_xhci;
> +	int ret = 0;
> +
> +	ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
> +	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
> +
> +	ret = board_usb_init(index, USB_INIT_HOST);
> +	if (ret != 0) {
> +		puts("Failed to initialize board for USB\n");
> +		return ret;
> +	}
> +
> +	ret = zynqmp_xhci_core_init(ctx);
> +	if (ret < 0) {
> +		puts("Failed to initialize xhci\n");
> +		return ret;
> +	}
> +
> +	*hccr = (struct xhci_hccr *)ctx->hcd;
> +	*hcor = (struct xhci_hcor *)((uint32_t) *hccr
> +				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> +	debug("zynqmp-xhci: init hccr %x and hcor %x hc_length %d\n",
> +	      (uint32_t)*hccr, (uint32_t)*hcor,
> +	      (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
> +
> +	return ret;
> +}
> +
> +void xhci_hcd_stop(int index)
> +{
> +	struct zynqmp_xhci *ctx = &zynqmp_xhci;
> +
> +	zynqmp_xhci_core_exit(ctx);
> +}
> diff --git a/include/linux/usb/xhci-zynqmp.h
> b/include/linux/usb/xhci-zynqmp.h new file mode 100644
> index 0000000..c384f91
> --- /dev/null
> +++ b/include/linux/usb/xhci-zynqmp.h
> @@ -0,0 +1,56 @@

You should just wrap all of this header into the xhci-zynqmp.c and be
done with it, no need for ad-hoc file.

> +/*
> + * Copyright 2015 Xilinx, Inc.
> + *
> + * Zynq USB HOST xHCI Controller
> + *
> + * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
> + *
> + * This file was resused from Freescale USB xHCI
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef _ASM_ARCH_XHCI_ZYNQMP_H_
> +#define _ASM_ARCH_XHCI_ZYNQMP_H_
> +
> +/* Default to the FSL XHCI defines */

FSL XHCI ? Really now, I thought this was a xilinx chip.

> +#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
> +#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
> +#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
> +#define USB3_PHY_RX_POWERON		BIT(14)
> +#define USB3_PHY_TX_POWERON		BIT(15)
> +#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | 
USB3_PHY_TX_POWERON)
> +#define USB3_PWRCTL_CLK_CMD_SHIFT   14
> +#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
> +
> +/* USBOTGSS_WRAPPER definitions */
> +#define USBOTGSS_WRAPRESET	BIT(17)
> +#define USBOTGSS_DMADISABLE BIT(16)
> +#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
> +#define USBOTGSS_STANDBYMODE_SMRT		BIT(5)
> +#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
> +#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
> +#define USBOTGSS_IDLEMODE_SMRT BIT(3)
> +#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
> +
> +/* USBOTGSS_IRQENABLE_SET_0 bit */
> +#define USBOTGSS_COREIRQ_EN	BIT(1)
> +
> +/* USBOTGSS_IRQENABLE_SET_1 bits */
> +#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	BIT(1)
> +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	BIT(3)
> +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	BIT(4)
> +#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	BIT(5)
> +#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	BIT(8)
> +#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	BIT(11)
> +#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	BIT(12)
> +#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	BIT(13)
> +#define USBOTGSS_IRQ_SET_1_OEVT_EN		BIT(16)
> +#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	BIT(17)
> +
> +struct zynqmp_xhci {
> +	struct xhci_hccr *hcd;
> +	struct dwc3 *dwc3_reg;

This definitelly should not be in a header file.

> +};
> +
> +#endif /* _ASM_ARCH_XHCI_ZYNQMP_H_ */