[U-Boot] [PATCH RESEND 5/7] spi: cadence_qspi: fix indirect read/write start address

Vikas Manocha
2015-06-17T02:14:23Z

Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
drivers/spi/cadence_qspi_apb.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e1e1315..7be67a9 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -647,7 +647,8 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,

/* Get address */
addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
- writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+ writel((u32)plat->ahbbase + addr_value,
+ plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);

/* The remaining lenght is dummy bytes. */
dummy_bytes = cmdlen - addr_bytes - 1;
@@ -741,7 +742,8 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,

/* Setup write address. */
reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
- writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+ writel((u32)plat->ahbbase + reg,
+ plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);

reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
--
1.7.9.5