From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Wed, 12 Aug 2015 23:18:15 +0200 Subject: [U-Boot] [PATCH] mxs_ocotp: Shift the HBUS divider correctly In-Reply-To: <1436706011-6233-1-git-send-email-marex@denx.de> References: <1436706011-6233-1-git-send-email-marex@denx.de> Message-ID: <55CBB817.6020102@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12/07/2015 15:00, Marek Vasut wrote: > From: Chris Smith > > When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() > for the purpose or restoring it back later, the value is not shifted by the > HBUS divider offset in that register. This is not a problem, since the shift > is zero on all MXS hardware. Add the shift anyway, for completeness and in > case FSL ever decides to re-use this driver on future designs. > > Signed-off-by: Chris Smith > Signed-off-by: Marek Vasut > Cc: Fabio Estevam > Cc: Stefano Babic > --- > drivers/misc/mxs_ocotp.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/misc/mxs_ocotp.c b/drivers/misc/mxs_ocotp.c > index 6f0a1d3..6c0d247 100644 > --- a/drivers/misc/mxs_ocotp.c > +++ b/drivers/misc/mxs_ocotp.c > @@ -152,6 +152,7 @@ static int mxs_ocotp_scale_hclk(bool enter, uint32_t *val) > /* Return the original HCLK clock speed. */ > *val = readl(&clkctrl_regs->hw_clkctrl_hbus); > *val &= CLKCTRL_HBUS_DIV_MASK; > + *val >>= CLKCTRL_HBUS_DIV_OFFSET; > > /* Scale the HCLK to 454/19 = 23.9 MHz . */ > scale_val = (~19) << CLKCTRL_HBUS_DIV_OFFSET; > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================