* [U-Boot] [PATCH v3 1/7] armv8: New MMU setup code allowing to use 48+ bits PA/VA
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
@ 2015-08-13 15:14 ` Sergey Temerkhanov
2015-08-13 15:28 ` York Sun
2015-08-13 15:14 ` [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure Sergey Temerkhanov
` (6 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:14 UTC (permalink / raw)
To: u-boot
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3:
- Reduced code duplication
- Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
- Moved 'reset_sctrl' call to the 'reset' label
- Rebased to the actual upstream tree
- Documented newly added config options
Changes in v2:
- Changed code licensing
- Completed the patchset
arch/arm/cpu/armv8/cache_v8.c | 80 +++++++++++++++++++++++++++++++++++++-
arch/arm/cpu/armv8/start.S | 36 +++++++++++++++++
arch/arm/include/asm/armv8/mmu.h | 79 ++++++++++++++++++++++++++++++++++---
arch/arm/include/asm/global_data.h | 1 +
arch/arm/include/asm/system.h | 7 ++++
arch/arm/lib/board.c | 6 ++-
doc/README.arm64 | 35 ++++++++++++++---
7 files changed, 229 insertions(+), 15 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c22f7b6..00778f2 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,6 +12,69 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_SYS_FULL_VA
+static void set_ptl1_entry(u64 index, u64 ptl2_entry)
+{
+ u64 *pgd = (u64 *)gd->arch.tlb_addr;
+ u64 value;
+
+ value = ptl2_entry | PTL1_TYPE_TABLE;
+ pgd[index] = value;
+}
+
+static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type)
+{
+ u64 *pmd = (u64 *)ptl1;
+ u64 value;
+
+ value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ pmd[bfn] = value;
+}
+
+static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
+
+#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
+#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+
+static void setup_pgtables(void)
+{
+ int l1_e, l2_e;
+ unsigned long pmd = 0;
+ unsigned long address;
+
+ /* Setup the PMD pointers */
+ for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
+ gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +
+ PTL1_ENTRIES * sizeof(u64);
+ gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
+ gd->arch.pmd_addr[l1_e] += 0xffffUL;
+ gd->arch.pmd_addr[l1_e] &= ~0xffffUL;
+ }
+
+ /* Setup the page tables */
+ for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
+ if (mem_map[pmd].base ==
+ (uintptr_t)l1_e << PTL2_BITS) {
+ set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);
+
+ for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {
+ address = mem_map[pmd].base
+ + (uintptr_t)l2_e * BLOCK_SIZE;
+ set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,
+ address, mem_map[pmd].attrs);
+ }
+
+ pmd++;
+ } else {
+ set_ptl1_entry(l1_e, 0);
+ }
+ }
+}
+
+#else
+
void set_pgtable_section(u64 *page_table, u64 index, u64 section,
u64 memory_type)
{
@@ -22,13 +85,25 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section,
page_table[index] = value;
}
+#endif
+
+
/* to activate the MMU we need to set up virtual memory */
static void mmu_setup(void)
{
+#ifndef CONFIG_SYS_FULL_VA
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
+#endif
int el;
+#ifdef CONFIG_SYS_FULL_VA
+ unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK;
+
+ /* Set up page tables only on BSP */
+ if (coreid == BSP_COREID)
+ setup_pgtables();
+#else
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
set_pgtable_section(page_table, i, i << SECTION_SHIFT,
@@ -45,7 +120,7 @@ static void mmu_setup(void)
MT_NORMAL);
}
}
-
+#endif
/* load TTBR0 */
el = current_el();
if (el == 1) {
@@ -145,6 +220,7 @@ u64 *__weak arch_get_page_table(void) {
return NULL;
}
+#ifndef CONFIG_SYS_FULL_VA
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
@@ -170,6 +246,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
flush_dcache_range(start, end);
asm volatile("dsb sy");
}
+#endif
+
#else /* CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e70bed4..a7dfe23 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -43,6 +43,9 @@ _bss_end_ofs:
.quad __bss_end - _start
reset:
+#ifdef CONFIG_SYS_RESET_SCTRL
+ bl reset_sctrl
+#endif
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
@@ -97,6 +100,39 @@ master_cpu:
bl _main
+#ifdef CONFIG_SYS_RESET_SCTRL
+reset_sctrl:
+ switch_el x1, 3f, 2f, 1f
+3:
+ mrs x0, sctlr_el3
+ b 0f
+2:
+ mrs x0, sctlr_el2
+ b 0f
+1:
+ mrs x0, sctlr_el1
+
+0:
+ ldr x1, =0xfdfffffa
+ and x0, x0, x1
+
+ switch_el x1, 6f, 5f, 4f
+6:
+ msr sctlr_el3, x0
+ b 7f
+5:
+ msr sctlr_el2, x0
+ b 7f
+4:
+ msr sctlr_el1, x0
+
+7:
+ dsb sy
+ isb
+ b __asm_invalidate_tlb_all
+ ret
+#endif
+
/*-----------------------------------------------------------------------*/
WEAK(apply_core_errata)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 04fa0be..a5176ba 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -21,7 +21,13 @@
* The following definitions are related each other, shoud be
* calculated specifically.
*/
+
+#ifndef CONFIG_SYS_FULL_VA
#define VA_BITS (42) /* 42 bits virtual address */
+#else
+#define VA_BITS CONFIG_SYS_VA_BITS
+#define PTL1_BITS CONFIG_SYS_PTL1_BITS
+#endif
/* PAGE_SHIFT determines the page size */
#undef PAGE_SIZE
@@ -30,11 +36,18 @@
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
- * section address mask and size definitions.
+ * block/section address mask and size definitions.
*/
+#ifndef CONFIG_SYS_FULL_VA
#define SECTION_SHIFT 29
#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
#define SECTION_MASK (~(SECTION_SIZE-1))
+#else
+#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT
+#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT)
+#define BLOCK_MASK (~(BLOCK_SIZE-1))
+#endif
+
/***************************************************************/
/*
@@ -46,15 +59,51 @@
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
-#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
- (0x04 << (MT_DEVICE_NGNRE*8)) | \
- (0x0c << (MT_DEVICE_GRE*8)) | \
- (0x44 << (MT_NORMAL_NC*8)) | \
- (UL(0xff) << (MT_NORMAL*8)))
+#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
+ (0x04 << (MT_DEVICE_NGNRE * 8)) | \
+ (0x0c << (MT_DEVICE_GRE * 8)) | \
+ (0x44 << (MT_NORMAL_NC * 8)) | \
+ (UL(0xff) << (MT_NORMAL * 8)))
/*
* Hardware page table definitions.
*
+ */
+
+#ifdef CONFIG_SYS_FULL_VA
+/*
+ * Level 1 descriptor (PGD).
+ */
+
+#define PTL1_TYPE_MASK (3 << 0)
+#define PTL1_TYPE_TABLE (3 << 0)
+
+#define PTL1_TABLE_PXN (1UL << 59)
+#define PTL1_TABLE_XN (1UL << 60)
+#define PTL1_TABLE_AP (1UL << 61)
+#define PTL1_TABLE_NS (1UL << 63)
+
+
+/*
+ * Level 2 descriptor (PMD).
+ */
+
+#define PTL2_TYPE_MASK (3 << 0)
+#define PTL2_TYPE_FAULT (0 << 0)
+#define PTL2_TYPE_TABLE (3 << 0)
+#define PTL2_TYPE_BLOCK (1 << 0)
+
+/*
+ * Block
+ */
+#define PTL2_BLOCK_S (3 << 8)
+#define PTL2_BLOCK_AF (1 << 10)
+#define PTL2_BLOCK_NG (1 << 11)
+#define PTL2_BLOCK_PXN (UL(1) << 53)
+#define PTL2_BLOCK_UXN (UL(1) << 54)
+
+#else
+/*
* Level 2 descriptor (PMD).
*/
#define PMD_TYPE_MASK (3 << 0)
@@ -72,6 +121,8 @@
#define PMD_SECT_PXN (UL(1) << 53)
#define PMD_SECT_UXN (UL(1) << 54)
+#endif
+
/*
* AttrIndx[2:0]
*/
@@ -98,9 +149,16 @@
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
+
+#ifndef CONFIG_SYS_FULL_VA
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
+#else
+#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS
+#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS
+#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS
+#endif
/* PTWs cacheable, inner/outer WBWA and non-shareable */
#define TCR_FLAGS (TCR_TG0_64K | \
@@ -110,8 +168,10 @@
TCR_T0SZ(VA_BITS))
#ifndef __ASSEMBLY__
+#ifndef CONFIG_SYS_FULL_VA
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type);
+#endif
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
asm volatile("dsb sy");
@@ -132,5 +192,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
}
asm volatile("isb");
}
+
+struct mm_region {
+ u64 base;
+ u64 size;
+ u64 attrs;
+};
#endif
+
#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 4e3ea55..723539c 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -38,6 +38,7 @@ struct arch_global_data {
unsigned long long timer_reset_value;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
+ unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES];
unsigned long tlb_size;
#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 868ea54..9803686 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -14,7 +14,12 @@
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
+#ifndef CONFIG_SYS_FULL_VA
#define PGTABLE_SIZE (0x10000)
+#else
+#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE
+#endif
+
/* 2MB granularity */
#define MMU_SECTION_SHIFT 21
@@ -136,7 +141,9 @@ void flush_l3_cache(void);
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
+#ifndef PGTABLE_SIZE
#define PGTABLE_SIZE (4096 * 4)
+#endif
/*
* This is used to ensure the compiler did actually allocate the register we
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 37ea6e9..0c9c66a 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -327,10 +327,12 @@ void board_init_f(ulong bootflag)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
- addr -= gd->arch.tlb_size;
+ gd->arch.tlb_size += 0xffff;
+ gd->arch.tlb_size &= ~(0x10000 - 1);
- /* round down to next 64 kB limit */
+ addr -= gd->arch.tlb_size;
addr &= ~(0x10000 - 1);
+ /* round down to next 64 kB limit */
gd->arch.tlb_addr = addr;
debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
diff --git a/doc/README.arm64 b/doc/README.arm64
index 75586db..f32108f 100644
--- a/doc/README.arm64
+++ b/doc/README.arm64
@@ -36,11 +36,34 @@ Notes
6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
aarch32 specific codes.
+7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores
+ supporting 64k pages it allows usage of full 48+ virtual/physical addresses
+
+ Enabling this option requires the following ones to be defined:
+ - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the
+ system memory map (start, length, attributes)
+ - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP
+ - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries
+ - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries
+ for the largest CONFIG_SYS_MEM_MAP entry
+ - CONFIG_COREID_MASK - the mask value used to get the core from the
+ MPIDR_EL1 register
+ - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level
+ page tables
+ - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block
+ entry from L2 page tables
+ - CONFIG_SYS_PGTABLE_SIZE - total size of the page table
+ - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3}
+
+
+
+
Contributor
===========
- Tom Rini <trini@ti.com>
- Scott Wood <scottwood@freescale.com>
- York Sun <yorksun@freescale.com>
- Simon Glass <sjg@chromium.org>
- Sharma Bhupesh <bhupesh.sharma@freescale.com>
- Rob Herring <robherring2@gmail.com>
+ Tom Rini <trini@ti.com>
+ Scott Wood <scottwood@freescale.com>
+ York Sun <yorksun@freescale.com>
+ Simon Glass <sjg@chromium.org>
+ Sharma Bhupesh <bhupesh.sharma@freescale.com>
+ Rob Herring <robherring2@gmail.com>
+ Sergey Temerkhanov <s.temerkhanov@gmail.com>
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 1/7] armv8: New MMU setup code allowing to use 48+ bits PA/VA
2015-08-13 15:14 ` [U-Boot] [PATCH v3 1/7] armv8: New MMU setup code allowing to use 48+ bits PA/VA Sergey Temerkhanov
@ 2015-08-13 15:28 ` York Sun
0 siblings, 0 replies; 14+ messages in thread
From: York Sun @ 2015-08-13 15:28 UTC (permalink / raw)
To: u-boot
On 08/13/2015 08:14 AM, Sergey Temerkhanov wrote:
> This patch adds code which sets up 2-level page tables on ARM64 thus
> extending available VA space. CPUs implementing 64k translation
> granule are able to use direct PA-VA mapping of the whole 48 bit
> address space.
> It also adds the ability to reset the SCTRL register at the very beginning
> of execution to avoid interference from stale mappings set up by early
> firmware/loaders/etc.
>
> Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
>
> ---
>
> Changes in v3:
> - Reduced code duplication
> - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
> - Moved 'reset_sctrl' call to the 'reset' label
> - Rebased to the actual upstream tree
> - Documented newly added config options
>
> Changes in v2:
> - Changed code licensing
> - Completed the patchset
>
> arch/arm/cpu/armv8/cache_v8.c | 80 +++++++++++++++++++++++++++++++++++++-
> arch/arm/cpu/armv8/start.S | 36 +++++++++++++++++
> arch/arm/include/asm/armv8/mmu.h | 79 ++++++++++++++++++++++++++++++++++---
> arch/arm/include/asm/global_data.h | 1 +
> arch/arm/include/asm/system.h | 7 ++++
> arch/arm/lib/board.c | 6 ++-
> doc/README.arm64 | 35 ++++++++++++++---
> 7 files changed, 229 insertions(+), 15 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
> index c22f7b6..00778f2 100644
> --- a/arch/arm/cpu/armv8/cache_v8.c
> +++ b/arch/arm/cpu/armv8/cache_v8.c
> @@ -12,6 +12,69 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> #ifndef CONFIG_SYS_DCACHE_OFF
> +
> +#ifdef CONFIG_SYS_FULL_VA
> +static void set_ptl1_entry(u64 index, u64 ptl2_entry)
> +{
> + u64 *pgd = (u64 *)gd->arch.tlb_addr;
> + u64 value;
> +
> + value = ptl2_entry | PTL1_TYPE_TABLE;
> + pgd[index] = value;
> +}
> +
> +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type)
> +{
> + u64 *pmd = (u64 *)ptl1;
> + u64 value;
> +
> + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
> + value |= PMD_ATTRINDX(memory_type);
> + pmd[bfn] = value;
> +}
> +
> +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
> +
> +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
> +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
> +
> +static void setup_pgtables(void)
> +{
> + int l1_e, l2_e;
> + unsigned long pmd = 0;
> + unsigned long address;
> +
> + /* Setup the PMD pointers */
> + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) {
> + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr +
> + PTL1_ENTRIES * sizeof(u64);
> + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e;
> + gd->arch.pmd_addr[l1_e] += 0xffffUL;
> + gd->arch.pmd_addr[l1_e] &= ~0xffffUL;
> + }
> +
> + /* Setup the page tables */
> + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) {
> + if (mem_map[pmd].base ==
> + (uintptr_t)l1_e << PTL2_BITS) {
> + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]);
> +
> + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) {
> + address = mem_map[pmd].base
> + + (uintptr_t)l2_e * BLOCK_SIZE;
> + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e,
> + address, mem_map[pmd].attrs);
> + }
> +
> + pmd++;
> + } else {
> + set_ptl1_entry(l1_e, 0);
> + }
> + }
> +}
> +
> +#else
> +
> void set_pgtable_section(u64 *page_table, u64 index, u64 section,
> u64 memory_type)
> {
> @@ -22,13 +85,25 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section,
> page_table[index] = value;
> }
>
> +#endif
> +
> +
Sergey,
FYI, we have a patch under review[1], rewriting MMU code for Freescale ARMv8
SoCs. It doesn't conflict with your proposed change, but modifies the common
file cache_v8.c.
[1] http://patchwork.ozlabs.org/patch/502980/
York
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
2015-08-13 15:14 ` [U-Boot] [PATCH v3 1/7] armv8: New MMU setup code allowing to use 48+ bits PA/VA Sergey Temerkhanov
@ 2015-08-13 15:14 ` Sergey Temerkhanov
2015-08-14 18:56 ` Simon Glass
2015-08-13 15:14 ` [U-Boot] [PATCH v3 3/7] armv8: Add psci.h from the Linux kernel Sergey Temerkhanov
` (5 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:14 UTC (permalink / raw)
To: u-boot
This commit adds functions issuing calls to firmware. This allows
to use services such as PSCI provided by firmware, e.g. ATF
The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3:
- Fixed clobber lists (thanks to Corey)
Changes in v2: None
arch/arm/cpu/armv8/Makefile | 1 +
arch/arm/cpu/armv8/fwcall.c | 77 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/include/asm/system.h | 8 +++++
3 files changed, 86 insertions(+)
create mode 100644 arch/arm/cpu/armv8/fwcall.c
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 6466ebb..39a6ce7 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -14,6 +14,7 @@ obj-y += exceptions.o
obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
+obj-y += fwcall.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
new file mode 100644
index 0000000..ff0caba
--- /dev/null
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -0,0 +1,77 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/system.h>
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * void hvc_call(arg0, arg1...arg7)
+ *
+ * issue the hypervisor call
+ *
+ * x0~x7: argument list
+ */
+void hvc_call(struct pt_regs *args)
+{
+ asm volatile(
+ "ldr x0, %0\n"
+ "ldr x1, %1\n"
+ "ldr x2, %2\n"
+ "ldr x3, %3\n"
+ "ldr x4, %4\n"
+ "ldr x5, %5\n"
+ "ldr x6, %6\n"
+ "ldr x7, %7\n"
+ "hvc #0\n"
+ "str x0, %0\n"
+ "str x1, %1\n"
+ "str x2, %2\n"
+ "str x3, %3\n"
+ : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+ : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6]), "m" (args->regs[7])
+ : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
+
+/*
+ * void smc_call(arg0, arg1...arg7)
+ *
+ * issue the secure monitor call
+ *
+ * x0~x7: argument list
+ */
+
+void smc_call(struct pt_regs *args)
+{
+ asm volatile(
+ "ldr x0, %0\n"
+ "ldr x1, %1\n"
+ "ldr x2, %2\n"
+ "ldr x3, %3\n"
+ "ldr x4, %4\n"
+ "ldr x5, %5\n"
+ "ldr x6, %6\n"
+ "smc #0\n"
+ "str x0, %0\n"
+ "str x1, %1\n"
+ "str x2, %2\n"
+ "str x3, %3\n"
+ : "+m" (args->regs[0]), "+m" (args->regs[1]),
+ "+m" (args->regs[2]), "+m" (args->regs[3])
+ : "m" (args->regs[4]), "m" (args->regs[5]),
+ "m" (args->regs[6])
+ : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17");
+}
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9803686..6b21d90 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,9 @@
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
+#include <common.h>
+#include <linux/compiler.h>
+
#ifdef CONFIG_ARM64
/*
@@ -93,6 +96,11 @@ void smp_kick_all_cpus(void);
void flush_l3_cache(void);
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void hvc_call(struct pt_regs *args);
+void smc_call(struct pt_regs *args);
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure
2015-08-13 15:14 ` [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure Sergey Temerkhanov
@ 2015-08-14 18:56 ` Simon Glass
2015-08-15 1:45 ` Sergei Temerkhanov
0 siblings, 1 reply; 14+ messages in thread
From: Simon Glass @ 2015-08-14 18:56 UTC (permalink / raw)
To: u-boot
Hi,
On 13 August 2015 at 09:14, Sergey Temerkhanov <s.temerkhanov@gmail.com> wrote:
> This commit adds functions issuing calls to firmware. This allows
> to use services such as PSCI provided by firmware, e.g. ATF
What is PSCI? ATF? SMC? What firmware? Please try to make your commit
message more helpful to people trying to understand the code you are
adding.
>
> The SMC call can destroy all registers declared temporary by the
> calling conventions. The clobber list is "x0..x17" because of
> this
>
> Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
>
> ---
>
> Changes in v3:
> - Fixed clobber lists (thanks to Corey)
>
> Changes in v2: None
>
> arch/arm/cpu/armv8/Makefile | 1 +
> arch/arm/cpu/armv8/fwcall.c | 77 +++++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/system.h | 8 +++++
> 3 files changed, 86 insertions(+)
> create mode 100644 arch/arm/cpu/armv8/fwcall.c
>
> diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> index 6466ebb..39a6ce7 100644
> --- a/arch/arm/cpu/armv8/Makefile
> +++ b/arch/arm/cpu/armv8/Makefile
> @@ -14,6 +14,7 @@ obj-y += exceptions.o
> obj-y += cache.o
> obj-y += tlb.o
> obj-y += transition.o
> +obj-y += fwcall.o
>
> obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
> obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
> diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
> new file mode 100644
> index 0000000..ff0caba
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fwcall.c
> @@ -0,0 +1,77 @@
> +/**
> + * (C) Copyright 2014, Cavium Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> +**/
> +
> +#include <asm-offsets.h>
> +#include <config.h>
> +#include <version.h>
> +#include <asm/macro.h>
> +#include <asm/system.h>
> +
> +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
> +
> +/*
> + * void hvc_call(arg0, arg1...arg7)
> + *
> + * issue the hypervisor call
> + *
> + * x0~x7: argument list
> + */
> +void hvc_call(struct pt_regs *args)
> +{
> + asm volatile(
> + "ldr x0, %0\n"
> + "ldr x1, %1\n"
> + "ldr x2, %2\n"
> + "ldr x3, %3\n"
> + "ldr x4, %4\n"
> + "ldr x5, %5\n"
> + "ldr x6, %6\n"
> + "ldr x7, %7\n"
> + "hvc #0\n"
> + "str x0, %0\n"
> + "str x1, %1\n"
> + "str x2, %2\n"
> + "str x3, %3\n"
> + : "+m" (args->regs[0]), "+m" (args->regs[1]),
> + "+m" (args->regs[2]), "+m" (args->regs[3])
> + : "m" (args->regs[4]), "m" (args->regs[5]),
> + "m" (args->regs[6]), "m" (args->regs[7])
> + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
> + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
> + "x16", "x17");
> +}
> +
> +/*
> + * void smc_call(arg0, arg1...arg7)
> + *
> + * issue the secure monitor call
> + *
> + * x0~x7: argument list
> + */
> +
> +void smc_call(struct pt_regs *args)
> +{
> + asm volatile(
> + "ldr x0, %0\n"
> + "ldr x1, %1\n"
> + "ldr x2, %2\n"
> + "ldr x3, %3\n"
> + "ldr x4, %4\n"
> + "ldr x5, %5\n"
> + "ldr x6, %6\n"
> + "smc #0\n"
> + "str x0, %0\n"
> + "str x1, %1\n"
> + "str x2, %2\n"
> + "str x3, %3\n"
> + : "+m" (args->regs[0]), "+m" (args->regs[1]),
> + "+m" (args->regs[2]), "+m" (args->regs[3])
> + : "m" (args->regs[4]), "m" (args->regs[5]),
> + "m" (args->regs[6])
> + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
> + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
> + "x16", "x17");
> +}
> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
> index 9803686..6b21d90 100644
> --- a/arch/arm/include/asm/system.h
> +++ b/arch/arm/include/asm/system.h
> @@ -1,6 +1,9 @@
> #ifndef __ASM_ARM_SYSTEM_H
> #define __ASM_ARM_SYSTEM_H
>
> +#include <common.h>
> +#include <linux/compiler.h>
> +
> #ifdef CONFIG_ARM64
>
> /*
> @@ -93,6 +96,11 @@ void smp_kick_all_cpus(void);
>
> void flush_l3_cache(void);
>
> +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
> +
> +void hvc_call(struct pt_regs *args);
> +void smc_call(struct pt_regs *args);
Please add comments here. What do these functions do? What does hvc
stand for. You can use something like:
/**
* hvc_call() - do a hypervisor call
*
* hvc is ...
*
* @args: Contains register values to pass in (and pass out??)
*
*/
> +
> #endif /* __ASSEMBLY__ */
>
> #else /* CONFIG_ARM64 */
> --
> 2.2.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure
2015-08-14 18:56 ` Simon Glass
@ 2015-08-15 1:45 ` Sergei Temerkhanov
2015-08-15 13:10 ` Simon Glass
0 siblings, 1 reply; 14+ messages in thread
From: Sergei Temerkhanov @ 2015-08-15 1:45 UTC (permalink / raw)
To: u-boot
On Fri, Aug 14, 2015 at 9:56 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi,
>
> On 13 August 2015 at 09:14, Sergey Temerkhanov <s.temerkhanov@gmail.com> wrote:
>> This commit adds functions issuing calls to firmware. This allows
>> to use services such as PSCI provided by firmware, e.g. ATF
>
> What is PSCI? ATF? SMC? What firmware? Please try to make your commit
> message more helpful to people trying to understand the code you are
> adding.
>
These abbreviations have been introduced by ARM and are used in their
docs. These
functions basically issue calls to the secure monitor (SMC) or
hypervisor (HVC). PSCI
is the Power State Coordination Interface and ATF is ARM Trusted Firmware. SMC/
HVC calls conform to the Calling Convention specification. I'll add
the comments to the
next version of this patch
>>
>> The SMC call can destroy all registers declared temporary by the
>> calling conventions. The clobber list is "x0..x17" because of
>> this
>>
>> Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
>> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
>>
>> ---
>>
>> Changes in v3:
>> - Fixed clobber lists (thanks to Corey)
>>
>> Changes in v2: None
>>
>> arch/arm/cpu/armv8/Makefile | 1 +
>> arch/arm/cpu/armv8/fwcall.c | 77 +++++++++++++++++++++++++++++++++++++++++++
>> arch/arm/include/asm/system.h | 8 +++++
>> 3 files changed, 86 insertions(+)
>> create mode 100644 arch/arm/cpu/armv8/fwcall.c
>>
>> diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
>> index 6466ebb..39a6ce7 100644
>> --- a/arch/arm/cpu/armv8/Makefile
>> +++ b/arch/arm/cpu/armv8/Makefile
>> @@ -14,6 +14,7 @@ obj-y += exceptions.o
>> obj-y += cache.o
>> obj-y += tlb.o
>> obj-y += transition.o
>> +obj-y += fwcall.o
>>
>> obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
>> obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
>> diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
>> new file mode 100644
>> index 0000000..ff0caba
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fwcall.c
>> @@ -0,0 +1,77 @@
>> +/**
>> + * (C) Copyright 2014, Cavium Inc.
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> +**/
>> +
>> +#include <asm-offsets.h>
>> +#include <config.h>
>> +#include <version.h>
>> +#include <asm/macro.h>
>> +#include <asm/system.h>
>> +
>> +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
>> +
>> +/*
>> + * void hvc_call(arg0, arg1...arg7)
>> + *
>> + * issue the hypervisor call
>> + *
>> + * x0~x7: argument list
>> + */
>> +void hvc_call(struct pt_regs *args)
>> +{
>> + asm volatile(
>> + "ldr x0, %0\n"
>> + "ldr x1, %1\n"
>> + "ldr x2, %2\n"
>> + "ldr x3, %3\n"
>> + "ldr x4, %4\n"
>> + "ldr x5, %5\n"
>> + "ldr x6, %6\n"
>> + "ldr x7, %7\n"
>> + "hvc #0\n"
>> + "str x0, %0\n"
>> + "str x1, %1\n"
>> + "str x2, %2\n"
>> + "str x3, %3\n"
>> + : "+m" (args->regs[0]), "+m" (args->regs[1]),
>> + "+m" (args->regs[2]), "+m" (args->regs[3])
>> + : "m" (args->regs[4]), "m" (args->regs[5]),
>> + "m" (args->regs[6]), "m" (args->regs[7])
>> + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
>> + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
>> + "x16", "x17");
>> +}
>> +
>> +/*
>> + * void smc_call(arg0, arg1...arg7)
>> + *
>> + * issue the secure monitor call
>> + *
>> + * x0~x7: argument list
>> + */
>> +
>> +void smc_call(struct pt_regs *args)
>> +{
>> + asm volatile(
>> + "ldr x0, %0\n"
>> + "ldr x1, %1\n"
>> + "ldr x2, %2\n"
>> + "ldr x3, %3\n"
>> + "ldr x4, %4\n"
>> + "ldr x5, %5\n"
>> + "ldr x6, %6\n"
>> + "smc #0\n"
>> + "str x0, %0\n"
>> + "str x1, %1\n"
>> + "str x2, %2\n"
>> + "str x3, %3\n"
>> + : "+m" (args->regs[0]), "+m" (args->regs[1]),
>> + "+m" (args->regs[2]), "+m" (args->regs[3])
>> + : "m" (args->regs[4]), "m" (args->regs[5]),
>> + "m" (args->regs[6])
>> + : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
>> + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
>> + "x16", "x17");
>> +}
>> diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
>> index 9803686..6b21d90 100644
>> --- a/arch/arm/include/asm/system.h
>> +++ b/arch/arm/include/asm/system.h
>> @@ -1,6 +1,9 @@
>> #ifndef __ASM_ARM_SYSTEM_H
>> #define __ASM_ARM_SYSTEM_H
>>
>> +#include <common.h>
>> +#include <linux/compiler.h>
>> +
>> #ifdef CONFIG_ARM64
>>
>> /*
>> @@ -93,6 +96,11 @@ void smp_kick_all_cpus(void);
>>
>> void flush_l3_cache(void);
>>
>> +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
>> +
>> +void hvc_call(struct pt_regs *args);
>> +void smc_call(struct pt_regs *args);
>
> Please add comments here. What do these functions do? What does hvc
> stand for. You can use something like:
>
> /**
> * hvc_call() - do a hypervisor call
> *
> * hvc is ...
> *
> * @args: Contains register values to pass in (and pass out??)
> *
> */
>
>> +
>> #endif /* __ASSEMBLY__ */
>>
>> #else /* CONFIG_ARM64 */
>> --
>> 2.2.0
>>
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure
2015-08-15 1:45 ` Sergei Temerkhanov
@ 2015-08-15 13:10 ` Simon Glass
0 siblings, 0 replies; 14+ messages in thread
From: Simon Glass @ 2015-08-15 13:10 UTC (permalink / raw)
To: u-boot
Hi Sergei,
On 14 August 2015 at 19:45, Sergei Temerkhanov <s.temerkhanov@gmail.com> wrote:
> On Fri, Aug 14, 2015 at 9:56 PM, Simon Glass <sjg@chromium.org> wrote:
>> Hi,
>>
>> On 13 August 2015 at 09:14, Sergey Temerkhanov <s.temerkhanov@gmail.com> wrote:
>>> This commit adds functions issuing calls to firmware. This allows
>>> to use services such as PSCI provided by firmware, e.g. ATF
>>
>> What is PSCI? ATF? SMC? What firmware? Please try to make your commit
>> message more helpful to people trying to understand the code you are
>> adding.
>>
>
> These abbreviations have been introduced by ARM and are used in their
> docs. These
> functions basically issue calls to the secure monitor (SMC) or
> hypervisor (HVC). PSCI
> is the Power State Coordination Interface and ATF is ARM Trusted Firmware. SMC/
> HVC calls conform to the Calling Convention specification. I'll add
> the comments to the
> next version of this patch
OK thanks. I think it is good to spell out abbreviations in Kconfig or
header files (e.g. the first time they are used).
Regards,
Simon
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 3/7] armv8: Add psci.h from the Linux kernel
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
2015-08-13 15:14 ` [U-Boot] [PATCH v3 1/7] armv8: New MMU setup code allowing to use 48+ bits PA/VA Sergey Temerkhanov
2015-08-13 15:14 ` [U-Boot] [PATCH v3 2/7] armv8: Add SMC calls infrastructure Sergey Temerkhanov
@ 2015-08-13 15:14 ` Sergey Temerkhanov
2015-08-13 15:14 ` [U-Boot] [PATCH v3 4/7] arm: serial: Add ability to use pre-initialized UARTs Sergey Temerkhanov
` (4 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:14 UTC (permalink / raw)
To: u-boot
This commit adds the psci.h header file from Linux kernel
which contains definitions related to the PSCI interface provided
by firmware
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3: None
Changes in v2: None
include/linux/psci.h | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 include/linux/psci.h
diff --git a/include/linux/psci.h b/include/linux/psci.h
new file mode 100644
index 0000000..310d83e
--- /dev/null
+++ b/include/linux/psci.h
@@ -0,0 +1,90 @@
+/*
+ * ARM Power State and Coordination Interface (PSCI) header
+ *
+ * This header holds common PSCI defines and macros shared
+ * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
+ *
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Anup Patel <anup.patel@linaro.org>
+ */
+
+#ifndef _UAPI_LINUX_PSCI_H
+#define _UAPI_LINUX_PSCI_H
+
+/*
+ * PSCI v0.1 interface
+ *
+ * The PSCI v0.1 function numbers are implementation defined.
+ *
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE 0x84000000
+#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT 0x40000000
+#define PSCI_0_2_FN64_BASE \
+ (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
+
+/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
+#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
+#define PSCI_0_2_POWER_STATE_ID_SHIFT 0
+#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16
+#define PSCI_0_2_POWER_STATE_TYPE_MASK \
+ (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
+#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24
+#define PSCI_0_2_POWER_STATE_AFFL_MASK \
+ (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
+
+/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
+#define PSCI_0_2_AFFINITY_LEVEL_ON 0
+#define PSCI_0_2_AFFINITY_LEVEL_OFF 1
+#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2
+
+/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
+#define PSCI_0_2_TOS_UP_MIGRATE 0
+#define PSCI_0_2_TOS_UP_NO_MIGRATE 1
+#define PSCI_0_2_TOS_MP 2
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT 16
+#define PSCI_VERSION_MINOR_MASK \
+ ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK
+#define PSCI_VERSION_MAJOR(ver) \
+ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver) \
+ ((ver) & PSCI_VERSION_MINOR_MASK)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS 0
+#define PSCI_RET_NOT_SUPPORTED -1
+#define PSCI_RET_INVALID_PARAMS -2
+#define PSCI_RET_DENIED -3
+#define PSCI_RET_ALREADY_ON -4
+#define PSCI_RET_ON_PENDING -5
+#define PSCI_RET_INTERNAL_FAILURE -6
+#define PSCI_RET_NOT_PRESENT -7
+#define PSCI_RET_DISABLED -8
+
+#endif /* _UAPI_LINUX_PSCI_H */
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 4/7] arm: serial: Add ability to use pre-initialized UARTs
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
` (2 preceding siblings ...)
2015-08-13 15:14 ` [U-Boot] [PATCH v3 3/7] armv8: Add psci.h from the Linux kernel Sergey Temerkhanov
@ 2015-08-13 15:14 ` Sergey Temerkhanov
2015-08-14 18:56 ` Simon Glass
2015-08-13 15:15 ` [U-Boot] [PATCH v3 5/7] armv8: cavium: Add ThunderX 88xx board definition Sergey Temerkhanov
` (3 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:14 UTC (permalink / raw)
To: u-boot
On some systems, UART initialization is performed before running U-Boot.
This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3:
- Added __used keyword
Changes in v2: None
drivers/serial/serial_pl01x.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index ad503af..f40c3ac 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -71,7 +71,7 @@ static int pl01x_tstc(struct pl01x_regs *regs)
return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
-static int pl01x_generic_serial_init(struct pl01x_regs *regs,
+static __used int pl01x_generic_serial_init(struct pl01x_regs *regs,
enum pl01x_type type)
{
switch (type) {
@@ -124,8 +124,9 @@ static int pl011_set_line_control(struct pl01x_regs *regs)
return 0;
}
-static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
- int clock, int baudrate)
+static int __used pl01x_generic_setbrg(struct pl01x_regs *regs,
+ enum pl01x_type type,
+ int clock, int baudrate)
{
switch (type) {
case TYPE_PL010: {
@@ -215,8 +216,10 @@ static void pl01x_serial_init_baud(int baudrate)
#endif
base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
+#ifndef CONFIG_PL010_SERIAL_PREINIT
pl01x_generic_serial_init(base_regs, pl01x_type);
pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
+#endif
}
/*
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 4/7] arm: serial: Add ability to use pre-initialized UARTs
2015-08-13 15:14 ` [U-Boot] [PATCH v3 4/7] arm: serial: Add ability to use pre-initialized UARTs Sergey Temerkhanov
@ 2015-08-14 18:56 ` Simon Glass
0 siblings, 0 replies; 14+ messages in thread
From: Simon Glass @ 2015-08-14 18:56 UTC (permalink / raw)
To: u-boot
Hi,
On 13 August 2015 at 09:14, Sergey Temerkhanov <s.temerkhanov@gmail.com> wrote:
> On some systems, UART initialization is performed before running U-Boot.
> This commit allows to skip UART re-initializaion on those systems
>
> Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
>
> ---
>
> Changes in v3:
> - Added __used keyword
>
> Changes in v2: None
>
> drivers/serial/serial_pl01x.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
Can you please use driver model for this board? Then you can add a
device tree option instead of another #ifdef. We should not be
updating the non-DM version of this code.
>
> diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
> index ad503af..f40c3ac 100644
> --- a/drivers/serial/serial_pl01x.c
> +++ b/drivers/serial/serial_pl01x.c
> @@ -71,7 +71,7 @@ static int pl01x_tstc(struct pl01x_regs *regs)
> return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
> }
>
> -static int pl01x_generic_serial_init(struct pl01x_regs *regs,
> +static __used int pl01x_generic_serial_init(struct pl01x_regs *regs,
> enum pl01x_type type)
> {
> switch (type) {
> @@ -124,8 +124,9 @@ static int pl011_set_line_control(struct pl01x_regs *regs)
> return 0;
> }
>
> -static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
> - int clock, int baudrate)
> +static int __used pl01x_generic_setbrg(struct pl01x_regs *regs,
> + enum pl01x_type type,
> + int clock, int baudrate)
> {
> switch (type) {
> case TYPE_PL010: {
> @@ -215,8 +216,10 @@ static void pl01x_serial_init_baud(int baudrate)
> #endif
> base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
>
> +#ifndef CONFIG_PL010_SERIAL_PREINIT
> pl01x_generic_serial_init(base_regs, pl01x_type);
> pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
> +#endif
> }
>
> /*
> --
> 2.2.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v3 5/7] armv8: cavium: Add ThunderX 88xx board definition
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
` (3 preceding siblings ...)
2015-08-13 15:14 ` [U-Boot] [PATCH v3 4/7] arm: serial: Add ability to use pre-initialized UARTs Sergey Temerkhanov
@ 2015-08-13 15:15 ` Sergey Temerkhanov
2015-08-13 15:15 ` [U-Boot] [PATCH v3 6/7] armv8: cavium: Add an implementation of ATF calling functions Sergey Temerkhanov
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:15 UTC (permalink / raw)
To: u-boot
This commit adds basic Cavium ThunderX 88xx board definitions and support.
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3:
- Fixed formatting
- Added MAINTAINERS
Changes in v2: None
arch/arm/Kconfig | 4 +
board/cavium/thunderx/Kconfig | 19 +++++
board/cavium/thunderx/MAINTAINERS | 6 ++
board/cavium/thunderx/Makefile | 8 ++
board/cavium/thunderx/thunderx.c | 59 +++++++++++++
configs/thunderx_88xx_defconfig | 3 +
include/configs/thunderx_88xx.h | 170 ++++++++++++++++++++++++++++++++++++++
7 files changed, 269 insertions(+)
create mode 100644 board/cavium/thunderx/Kconfig
create mode 100644 board/cavium/thunderx/MAINTAINERS
create mode 100644 board/cavium/thunderx/Makefile
create mode 100644 board/cavium/thunderx/thunderx.c
create mode 100644 configs/thunderx_88xx_defconfig
create mode 100644 include/configs/thunderx_88xx.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8b8269f..0c9f939 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -815,6 +815,9 @@ config TARGET_STM32F429_DISCOVERY
bool "Support STM32F429 Discovery"
select CPU_V7M
+config TARGET_THUNDERX_88XX
+ bool "Support ThunderX 88xx"
+
endchoice
source "arch/arm/mach-at91/Kconfig"
@@ -984,6 +987,7 @@ source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
source "board/zipitz2/Kconfig"
+source "board/cavium/thunderx/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig
new file mode 100644
index 0000000..3e62abf
--- /dev/null
+++ b/board/cavium/thunderx/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_THUNDERX_88XX
+
+config SYS_CPU
+ string
+ default "armv8"
+
+config SYS_BOARD
+ string
+ default "thunderx"
+
+config SYS_VENDOR
+ string
+ default "cavium"
+
+config SYS_CONFIG_NAME
+ string
+ default "thunderx_88xx"
+
+endif
diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS
new file mode 100644
index 0000000..c84d3b5
--- /dev/null
+++ b/board/cavium/thunderx/MAINTAINERS
@@ -0,0 +1,6 @@
+THUNDERX BOARD
+M: Sergey Temerkhanov <s.temerkhanov@gmail.com>
+S: Maintained
+F: board/cavium/thunderx/
+F: include/configs/thunderx_88xx.h
+F: configs/thunderx_88xx_defconfig
diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile
new file mode 100644
index 0000000..306044a
--- /dev/null
+++ b/board/cavium/thunderx/Makefile
@@ -0,0 +1,8 @@
+#
+#
+# (C) Copyright 2014, Cavium Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := thunderx.o
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
new file mode 100644
index 0000000..5a5e259
--- /dev/null
+++ b/board/cavium/thunderx/thunderx.c
@@ -0,0 +1,59 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Clear spin table so that secondary processors
+ * observe the correct value after waken up from wfe.
+ */
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+/*
+ * Board specific ethernet initialization routine.
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+
+ return rc;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ printf("DEBUG: PCI Init TODO *****\n");
+}
+#endif
+
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
new file mode 100644
index 0000000..79fa65a
--- /dev/null
+++ b/configs/thunderx_88xx_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="ARM64"
+CONFIG_ARM=y
+CONFIG_TARGET_THUNDERX_88XX=y
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
new file mode 100644
index 0000000..6428506
--- /dev/null
+++ b/include/configs/thunderx_88xx.h
@@ -0,0 +1,170 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __THUNDERX_88XX_H__
+#define __THUNDERX_88XX_H__
+
+#define CONFIG_REMAKE_ELF
+
+/*#define CONFIG_GICV3*/
+
+/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH
+
+/*#define CONFIG_SUPPORT_RAW_INITRD */
+
+
+#define CONFIG_IDENT_STRING \
+ " for Cavium Thunder CN88XX ARM v8 Multi-Core"
+#define CONFIG_BOOTP_VCI_STRING "Diagnostics"
+
+#define MEM_BASE 0x00500000
+
+#define CONFIG_COREID_MASK 0xffffff
+
+#define CONFIG_SYS_FULL_VA
+
+#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \
+ MT_NORMAL}, \
+ {0x800000000000UL, 0x40000000000UL, \
+ MT_DEVICE_NGNRNE}, \
+ {0x840000000000UL, 0x40000000000UL, \
+ MT_DEVICE_NGNRNE}, \
+ {0xffffffffffffUL, 0xfffffffffffUL, \
+ MT_DEVICE_NGNRNE},}
+
+#define CONFIG_SYS_MEM_MAP_SIZE 3
+
+#define CONFIG_SYS_VA_BITS 48
+#define CONFIG_SYS_PTL1_BITS 42
+#define CONFIG_SYS_BLOCK_SHIFT 29
+#define CONFIG_SYS_PTL1_ENTRIES 64
+#define CONFIG_SYS_PTL2_ENTRIES 8192
+
+#define CONFIG_SYS_PGTABLE_SIZE \
+ ((CONFIG_SYS_PTL1_ENTRIES + \
+ CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
+#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32)
+#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16)
+#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16)
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE 0x00500000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+
+#define CONFIG_SYS_MEMTEST_START MEM_BASE
+#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* PL011 Serial Configuration */
+
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX 0
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE (0x801000000000)
+#define GICR_BASE (0x801000002000)
+#define CONFIG_SYS_SERIAL0 0x87e024000000
+#define CONFIG_SYS_SERIAL1 0x87e025000000
+
+#define CONFIG_PL010_SERIAL_PREINIT
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_MENU
+/*#define CONFIG_MENU_SHOW*/
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SAVES
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+
+/* Initial environment variables */
+#define UBOOT_IMG_HEAD_SIZE 0x40
+/* C80000 - 0x40 */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr=08007ffc0\0" \
+ "fdt_addr=0x94C00000\0" \
+ "fdt_high=0x9fffffff\0"
+
+#define CONFIG_BOOTARGS \
+ "console=ttyAMA0,115200n8 " \
+ "earlycon=pl011,0x87e024000000 " \
+ "debug maxcpus=48 rootwait rw "\
+ "root=/dev/sda2 coherent_pool=16M"
+#define CONFIG_BOOTDELAY 5
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT "ThunderX_88XX> "
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+#define CONFIG_NO_RELOCATION 1
+#define CONFIG_LIB_RAND
+#define PLL_REF_CLK 50000000 /* 50 MHz */
+#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
+
+#endif /* __THUNDERX_88XX_H__ */
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 6/7] armv8: cavium: Add an implementation of ATF calling functions
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
` (4 preceding siblings ...)
2015-08-13 15:15 ` [U-Boot] [PATCH v3 5/7] armv8: cavium: Add ThunderX 88xx board definition Sergey Temerkhanov
@ 2015-08-13 15:15 ` Sergey Temerkhanov
2015-08-13 15:15 ` [U-Boot] [PATCH v3 7/7] armv8: cavium: Get DRAM size from ATF Sergey Temerkhanov
2015-08-13 16:29 ` [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergei Temerkhanov
7 siblings, 0 replies; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:15 UTC (permalink / raw)
To: u-boot
This commit adds functions issuing calls to the product-specific ATF
services
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3: None
Changes in v2: None
board/cavium/thunderx/Makefile | 2 +-
board/cavium/thunderx/atf.c | 312 ++++++++++++++++++++++++++++++++++++++++
include/cavium/atf.h | 22 +++
include/cavium/atf_part.h | 26 ++++
include/cavium/thunderx_svc.h | 67 +++++++++
include/configs/thunderx_88xx.h | 2 +
6 files changed, 430 insertions(+), 1 deletion(-)
create mode 100644 board/cavium/thunderx/atf.c
create mode 100644 include/cavium/atf.h
create mode 100644 include/cavium/atf_part.h
create mode 100644 include/cavium/thunderx_svc.h
diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile
index 306044a..c78c414 100644
--- a/board/cavium/thunderx/Makefile
+++ b/board/cavium/thunderx/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := thunderx.o
+obj-y := thunderx.o atf.o
diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c
new file mode 100644
index 0000000..6ab9de9
--- /dev/null
+++ b/board/cavium/thunderx/atf.c
@@ -0,0 +1,312 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/system.h>
+#include <cavium/thunderx_svc.h>
+#include <cavium/atf.h>
+#include <cavium/atf_part.h>
+
+#include <asm/psci.h>
+
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_MMC_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_NOR_READ;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_get_pcount(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_PART_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_GET_PART;
+ regs.regs[1] = (uintptr_t)part;
+ regs.regs[2] = index;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_erase_nor(uintptr_t offset, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_NOR_ERASE;
+ regs.regs[1] = offset;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_NOR_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = THUNDERX_MMC_WRITE;
+ regs.regs[1] = offset;
+ regs.regs[2] = size;
+ regs.regs[3] = (uintptr_t)buffer;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_dram_size(unsigned int node)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_DRAM_SIZE;
+ regs.regs[1] = node;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_node_count(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_NODE_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_env_count(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_ENV_COUNT;
+
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t atf_env_string(size_t index, char *str)
+{
+ uint64_t *buf = (void *)str;
+ struct pt_regs regs;
+ regs.regs[0] = THUNDERX_ENV_STRING;
+ regs.regs[1] = index;
+
+ smc_call(®s);
+
+ if (regs.regs > 0) {
+ buf[0] = regs.regs[0];
+ buf[1] = regs.regs[1];
+ buf[2] = regs.regs[2];
+ buf[3] = regs.regs[3];
+
+ return 1;
+ } else {
+ return regs.regs[0];
+ }
+}
+
+#ifdef CONFIG_CMD_ATF
+
+static void atf_print_ver(void)
+{
+ struct pt_regs regs;
+ regs.regs[0] = ARM_STD_SVC_VERSION;
+
+ smc_call(®s);
+
+ printf("ARM Std FW version: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+
+ regs.regs[0] = THUNDERX_SVC_VERSION;
+
+ smc_call(®s);
+
+ printf("ThunderX OEM ver: %ld.%ld\n", regs.regs[0], regs.regs[1]);
+}
+
+static void atf_print_uid(void)
+{
+}
+
+static void atf_print_part_table(void)
+{
+ size_t pcount;
+ unsigned long i;
+ int ret;
+ char *ptype;
+
+ struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE;
+
+ pcount = atf_get_pcount();
+
+ printf("Partition count: %lu\n\n", pcount);
+ printf("%10s %10s %10s\n", "Type", "Size", "Offset");
+
+ for (i = 0; i < pcount; i++) {
+ ret = atf_get_part(part, i);
+
+ if (ret < 0) {
+ printf("Uknown error while reading partition: %d\n",
+ ret);
+ return;
+ }
+
+ switch (part->type) {
+ case PARTITION_NBL1FW_REST:
+ ptype = "NBL1FW";
+ break;
+ case PARTITION_BL2_BL31:
+ ptype = "BL2_BL31";
+ break;
+ case PARTITION_UBOOT:
+ ptype = "BOOTLDR";
+ break;
+ case PARTITION_KERNEL:
+ ptype = "KERNEL";
+ break;
+ case PARTITION_DEVICE_TREE:
+ ptype = "DEVTREE";
+ break;
+ default:
+ ptype = "UNKNOWN";
+ }
+ printf("%10s %10d %10lx\n", ptype, part->size, part->offset);
+ }
+}
+
+int do_atf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ssize_t ret;
+ size_t size, offset;
+ void *buffer = 0;
+ unsigned int index, node;
+ char str[4 * sizeof(uint64_t)];
+
+ if ((argc == 5) && !strcmp(argv[1], "readmmc")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_read_mmc(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "readnor")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_read_nor(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "writemmc")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_write_mmc(offset, buffer, size);
+ } else if ((argc == 5) && !strcmp(argv[1], "writenor")) {
+ buffer = (void *)simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[3], NULL, 10);
+ size = simple_strtoul(argv[4], NULL, 10);
+
+ ret = atf_write_nor(offset, buffer, size);
+ } else if ((argc == 2) && !strcmp(argv[1], "part")) {
+ atf_print_part_table();
+ } else if ((argc == 4) && !strcmp(argv[1], "erasenor")) {
+ offset = simple_strtoul(argv[2], NULL, 10);
+ size = simple_strtoul(argv[3], NULL, 10);
+
+ ret = atf_erase_nor(offset, size);
+ } else if ((argc == 2) && !strcmp(argv[1], "envcount")) {
+ ret = atf_env_count();
+ printf("Number of environment strings: %zd\n", ret);
+ } else if ((argc == 3) && !strcmp(argv[1], "envstring")) {
+ index = simple_strtoul(argv[2], NULL, 10);
+ ret = atf_env_string(index, str);
+ if (ret > 0)
+ printf("Environment string %d: %s\n", index, str);
+ else
+ printf("Return code: %zd\n", ret);
+ } else if ((argc == 3) && !strcmp(argv[1], "dramsize")) {
+ node = simple_strtoul(argv[2], NULL, 10);
+ ret = atf_dram_size(node);
+ printf("DRAM size: %zd Mbytes\n", ret >> 20);
+ } else if ((argc == 2) && !strcmp(argv[1], "nodes")) {
+ ret = atf_node_count();
+ printf("Nodes count: %zd\n", ret);
+ } else if ((argc == 2) && !strcmp(argv[1], "ver")) {
+ atf_print_ver();
+ } else if ((argc == 2) && !strcmp(argv[1], "uid")) {
+ atf_print_uid();
+ } else {
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ atf, 10, 1, do_atf,
+ "issue calls to ATF",
+ "\t readmmc addr offset size - read MMC card\n"
+ "\t readnor addr offset size - read NOR flash\n"
+ "\t writemmc addr offset size - write MMC card\n"
+ "\t writenor addr offset size - write NOR flash\n"
+ "\t erasenor offset size - erase NOR flash\n"
+ "\t nodes - number of nodes\n"
+ "\t dramsize node - size of DRAM attached to node\n"
+ "\t envcount - number of environment strings\n"
+ "\t envstring index - print the environment string\n"
+ "\t part - print MMC partition table\n"
+ "\t ver - print ATF call set versions\n"
+);
+
+#endif
diff --git a/include/cavium/atf.h b/include/cavium/atf.h
new file mode 100644
index 0000000..0a53c2f
--- /dev/null
+++ b/include/cavium/atf.h
@@ -0,0 +1,22 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+#ifndef __ATF_H__
+#define __ATF_H__
+#include <cavium/atf_part.h>
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_get_pcount(void);
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index);
+ssize_t atf_erase_nor(uintptr_t offset, size_t size);
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_dram_size(unsigned int node);
+ssize_t atf_node_count(void);
+ssize_t atf_env_count(void);
+ssize_t atf_env_string(size_t index, char *str);
+
+#endif
diff --git a/include/cavium/atf_part.h b/include/cavium/atf_part.h
new file mode 100644
index 0000000..182f6f4
--- /dev/null
+++ b/include/cavium/atf_part.h
@@ -0,0 +1,26 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __ATF_PART_H__
+#define __ATF_PART_H__
+
+struct storage_partition {
+ unsigned int type;
+ unsigned int size;
+ unsigned long offset;
+};
+
+enum {
+ PARTITION_NBL1FW_REST = 0,
+ PARTITION_BL2_BL31 = 1,
+ PARTITION_UBOOT = 2,
+ PARTITION_UEFI = 2,
+ PARTITION_KERNEL = 3,
+ PARTITION_DEVICE_TREE = 4,
+ PARTITION_LAST,
+};
+
+#endif
diff --git a/include/cavium/thunderx_svc.h b/include/cavium/thunderx_svc.h
new file mode 100644
index 0000000..416ce3c
--- /dev/null
+++ b/include/cavium/thunderx_svc.h
@@ -0,0 +1,67 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#ifndef __THUNDERX_SVC_H__
+#define __THUNDERX_SVC_H__
+
+/* SMC function IDs for general purpose queries */
+
+#define THUNDERX_SVC_CALL_COUNT 0x4300ff00
+#define THUNDERX_SVC_UID 0x4300ff01
+
+#define THUNDERX_SVC_VERSION 0x4300ff03
+
+#define ARM_STD_SVC_VERSION 0x8400ff03
+
+/* ThunderX Service Calls version numbers */
+#define THUNDERX_VERSION_MAJOR 0x0
+#define THUNDERX_VERSION_MINOR 0x1
+
+#define THUNDERX_MMC_READ 0x43000101
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_MMC_WRITE 0x43000102
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+
+#define THUNDERX_NOR_READ 0x43000111
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_WRITE 0x43000112
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_ERASE 0x43000113
+/* x1 - block address
+ */
+
+#define THUNDERX_PART_COUNT 0x43000201
+#define THUNDERX_GET_PART 0x43000202
+/* x1 - pointer to the buffer
+ * x2 - index
+ */
+
+#define THUNDERX_DRAM_SIZE 0x43000301
+/* x1 - node number
+ */
+
+#define THUNDERX_GTI_SYNC 0x43000401
+
+#define THUNDERX_ENV_COUNT 0x43000501
+#define THUNDERX_ENV_STRING 0x43000502
+/* x1 - index
+ */
+
+#define THUNDERX_NODE_COUNT 0x43000601
+
+#endif /* __THUNDERX_SVC_H__ */
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 6428506..fd5a759 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -32,6 +32,8 @@
#define CONFIG_SYS_FULL_VA
+#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
+
#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \
MT_NORMAL}, \
{0x800000000000UL, 0x40000000000UL, \
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 7/7] armv8: cavium: Get DRAM size from ATF
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
` (5 preceding siblings ...)
2015-08-13 15:15 ` [U-Boot] [PATCH v3 6/7] armv8: cavium: Add an implementation of ATF calling functions Sergey Temerkhanov
@ 2015-08-13 15:15 ` Sergey Temerkhanov
2015-08-13 16:29 ` [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergei Temerkhanov
7 siblings, 0 replies; 14+ messages in thread
From: Sergey Temerkhanov @ 2015-08-13 15:15 UTC (permalink / raw)
To: u-boot
Change the dram_init() function on ThunderX to query ATF services for
the real installed DRAM size
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
---
Changes in v3: None
Changes in v2: None
board/cavium/thunderx/Makefile | 2 +-
board/cavium/thunderx/dram.c | 35 +++++++++++++++++++++++++++++++++++
board/cavium/thunderx/thunderx.c | 12 ------------
3 files changed, 36 insertions(+), 13 deletions(-)
create mode 100644 board/cavium/thunderx/dram.c
diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile
index c78c414..9200dd6 100644
--- a/board/cavium/thunderx/Makefile
+++ b/board/cavium/thunderx/Makefile
@@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := thunderx.o atf.o
+obj-y := thunderx.o atf.o dram.o
diff --git a/board/cavium/thunderx/dram.c b/board/cavium/thunderx/dram.c
new file mode 100644
index 0000000..858699d
--- /dev/null
+++ b/board/cavium/thunderx/dram.c
@@ -0,0 +1,35 @@
+/**
+ * (C) Copyright 2014, Cavium Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+**/
+
+#include <common.h>
+#include <cavium/atf.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ ssize_t node_count = atf_node_count();
+ ssize_t dram_size;
+ int node;
+
+ printf("Initializing\nNodes in system: %zd\n", node_count);
+
+ gd->ram_size = 0;
+
+ for (node = 0; node < node_count; node++) {
+ dram_size = atf_dram_size(node);
+ printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
+ gd->ram_size += dram_size;
+ }
+
+ gd->ram_size -= MEM_BASE;
+
+ *(unsigned long *)CPU_RELEASE_ADDR = 0;
+
+ puts("DRAM size:");
+
+ return 0;
+}
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index 5a5e259..a5cf7c5 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -16,18 +16,6 @@ int board_init(void)
return 0;
}
-int dram_init(void)
-{
- /*
- * Clear spin table so that secondary processors
- * observe the correct value after waken up from wfe.
- */
- *(unsigned long *)CPU_RELEASE_ADDR = 0;
-
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
int timer_init(void)
{
return 0;
--
2.2.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family
2015-08-13 15:14 [U-Boot] [PATCH v3 0/7] This patch series adds support for Cavium ThunderX 88xx SoC family Sergey Temerkhanov
` (6 preceding siblings ...)
2015-08-13 15:15 ` [U-Boot] [PATCH v3 7/7] armv8: cavium: Get DRAM size from ATF Sergey Temerkhanov
@ 2015-08-13 16:29 ` Sergei Temerkhanov
7 siblings, 0 replies; 14+ messages in thread
From: Sergei Temerkhanov @ 2015-08-13 16:29 UTC (permalink / raw)
To: u-boot
Please disregard, this patch series is incomplete
Regards,
Sergey
On Thu, Aug 13, 2015 at 6:14 PM, Sergey Temerkhanov <s.temerkhanov@gmail.com
> wrote:
> (http://cavium.com/ThunderX_ARM_Processors.html)
>
> Changes in v3:
> - Reduced code duplication
> - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS
> - Moved 'reset_sctrl' call to the 'reset' label
> - Rebased to the actual upstream tree
> - Documented newly added config options
> - Fixed clobber lists (thanks to Corey)
> - Added __used keyword
> - Fixed formatting
> - Added MAINTAINERS
>
> Changes in v2:
> - Changed code licensing
> - Completed the patchset
>
> Sergey Temerkhanov (7):
> armv8: New MMU setup code allowing to use 48+ bits PA/VA
> armv8: Add SMC calls infrastructure
> armv8: Add psci.h from the Linux kernel
> arm: serial: Add ability to use pre-initialized UARTs
> armv8: cavium: Add ThunderX 88xx board definition
> armv8: cavium: Add an implementation of ATF calling functions
> armv8: cavium: Get DRAM size from ATF
>
> arch/arm/Kconfig | 4 +
> arch/arm/cpu/armv8/Makefile | 1 +
> arch/arm/cpu/armv8/cache_v8.c | 80 +++++++++-
> arch/arm/cpu/armv8/fwcall.c | 77 +++++++++
> arch/arm/cpu/armv8/start.S | 36 +++++
> arch/arm/include/asm/armv8/mmu.h | 79 +++++++++-
> arch/arm/include/asm/global_data.h | 1 +
> arch/arm/include/asm/system.h | 15 ++
> arch/arm/lib/board.c | 6 +-
> board/cavium/thunderx/Kconfig | 19 +++
> board/cavium/thunderx/MAINTAINERS | 6 +
> board/cavium/thunderx/Makefile | 8 +
> board/cavium/thunderx/atf.c | 312
> +++++++++++++++++++++++++++++++++++++
> board/cavium/thunderx/dram.c | 35 +++++
> board/cavium/thunderx/thunderx.c | 47 ++++++
> configs/thunderx_88xx_defconfig | 3 +
> doc/README.arm64 | 35 ++++-
> drivers/serial/serial_pl01x.c | 9 +-
> include/cavium/atf.h | 22 +++
> include/cavium/atf_part.h | 26 ++++
> include/cavium/thunderx_svc.h | 67 ++++++++
> include/configs/thunderx_88xx.h | 172 ++++++++++++++++++++
> include/linux/psci.h | 90 +++++++++++
> 23 files changed, 1132 insertions(+), 18 deletions(-)
> create mode 100644 arch/arm/cpu/armv8/fwcall.c
> create mode 100644 board/cavium/thunderx/Kconfig
> create mode 100644 board/cavium/thunderx/MAINTAINERS
> create mode 100644 board/cavium/thunderx/Makefile
> create mode 100644 board/cavium/thunderx/atf.c
> create mode 100644 board/cavium/thunderx/dram.c
> create mode 100644 board/cavium/thunderx/thunderx.c
> create mode 100644 configs/thunderx_88xx_defconfig
> create mode 100644 include/cavium/atf.h
> create mode 100644 include/cavium/atf_part.h
> create mode 100644 include/cavium/thunderx_svc.h
> create mode 100644 include/configs/thunderx_88xx.h
> create mode 100644 include/linux/psci.h
>
> --
> 2.2.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread