From mboxrd@z Thu Jan 1 00:00:00 1970 From: vikasm Date: Thu, 13 Aug 2015 08:50:18 -0700 Subject: [U-Boot] [v2 1/6] spi: cadence_qspi: move trigger base configuration in init In-Reply-To: <201508130407.20129.marex@denx.de> References: <1437013654-29387-1-git-send-email-vikas.manocha@st.com> <1437013654-29387-2-git-send-email-vikas.manocha@st.com> <201508130407.20129.marex@denx.de> Message-ID: <55CCBCBA.1030203@st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Marek, On 08/12/2015 07:07 PM, Marek Vasut wrote: > On Thursday, July 16, 2015 at 04:27:29 AM, Vikas Manocha wrote: > > Commit message is missing. Actually subject of the mail was sufficient, this patch just moves the register configuration in init. > >> Signed-off-by: Vikas Manocha >> --- >> >> Changes in v2: Rebased to master >> >> drivers/spi/cadence_qspi_apb.c | 9 ++------- >> 1 file changed, 2 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/spi/cadence_qspi_apb.c >> b/drivers/spi/cadence_qspi_apb.c index d053407..1ae7edf 100644 >> --- a/drivers/spi/cadence_qspi_apb.c >> +++ b/drivers/spi/cadence_qspi_apb.c >> @@ -534,6 +534,8 @@ void cadence_qspi_apb_controller_init(struct >> cadence_spi_platdata *plat) >> >> /* Indirect mode configurations */ >> writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); >> + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), > > You can drop the parenthesis around the first argument, they're useless. > Also, the indent of the second arg should be fixed, I believe checkpatch > might even complain about it. ok. Rgds, Vikas > >> + plat->regbase + CQSPI_REG_INDIRECTTRIGGER); >> >> /* Disable all interrupts */ >> writel(0, plat->regbase + CQSPI_REG_IRQMASK); >> @@ -693,10 +695,6 @@ int cadence_qspi_apb_indirect_read_setup(struct >> cadence_spi_platdata *plat, /* for normal read (only ramtron as of now) */ >> addr_bytes = cmdlen - 1; >> >> - /* Setup the indirect trigger address */ >> - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), >> - plat->regbase + CQSPI_REG_INDIRECTTRIGGER); >> - >> /* Configure the opcode */ >> rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; >> >> @@ -790,9 +788,6 @@ int cadence_qspi_apb_indirect_write_setup(struct >> cadence_spi_platdata *plat, cmdlen, (unsigned int)cmdbuf); >> return -EINVAL; >> } >> - /* Setup the indirect trigger address */ >> - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), >> - plat->regbase + CQSPI_REG_INDIRECTTRIGGER); >> >> /* Configure the opcode */ >> reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; > > Best regards, > Marek Vasut > . >