From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 14 Aug 2015 09:12:05 -0700 Subject: [U-Boot] [PATCH] arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS In-Reply-To: <1438653337-47307-1-git-send-email-b18965@freescale.com> References: <1438653337-47307-1-git-send-email-b18965@freescale.com> Message-ID: <55CE1355.3060004@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 08/03/2015 06:55 PM, Alison Wang wrote: > This patch addresses a problem mentioned recently on this mailing list: > [1]. > > In that posting a LS1021 based system was locking up at about 5 minutes > after boot,but the problem was mysteriously related to the toolchain > used for building u-boot.Debugging the problem reveals a stuck > interrupt 29 on the GIC. > > It appears Freescale's LS1021 support in u-boot erroneously sets the > 64-bit ARM generic PL1 physical time CompareValue register to all-ones > with a 32-bit value.This causes the timer compare to fire 344 seconds > after u-boot configures it.Depending on how fast u-boot gets the > kernel booted,this amounts to about 5-minutes of Linux uptime before > locking up. > > Apparently the bug is masked by some toolchains. Perhaps this is > explained by default compiler options, word sizes, or binutils versions. > > To fix the above issue, the generic physical timer is disabled > before jumping to the OS. > > [1] > https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html > > Signed-off-by: Chris Kilgour > Signed-off-by: Alison Wang > --- > arch/arm/cpu/armv7/ls102xa/cpu.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c > index 75f0d8c..298422f 100644 > --- a/arch/arm/cpu/armv7/ls102xa/cpu.c > +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c > @@ -346,3 +346,13 @@ void smp_kick_all_cpus(void) > out_be32(&gur->brrl, 0x2); > } > #endif > + > +void arch_preboot_os(void) > +{ > + unsigned long ctrl; > + > + /* Disable PL1 Physical Timer */ > + asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl)); > + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; > + asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); > +} > Mark, Can you comment on this patch? I believe this is the follow-up after discussion here http://patchwork.ozlabs.org/patch/495476/. York