From mboxrd@z Thu Jan  1 00:00:00 1970
From: Sinan Akman <sinan@writeme.com>
Date: Fri, 14 Aug 2015 12:28:46 -0400
Subject: [U-Boot] [PATCH 2/3] LS102XA:workaround:disable priorities
 within DDR
In-Reply-To: <1439535264-41637-2-git-send-email-yao.yuan@freescale.com>
References: <1439535264-41637-1-git-send-email-yao.yuan@freescale.com>
 <1439535264-41637-2-git-send-email-yao.yuan@freescale.com>
Message-ID: <55CE173E.5090100@writeme.com>
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To: u-boot@lists.denx.de


   Hi Yuan

On 14/08/15 02:54 AM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
>
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on silicon Rev2.0.
>
> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
> ---
>   board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++-
>   board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++-
>   2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
> index 52bffc8..1256ece 100644
> --- a/board/freescale/ls1021aqds/ls1021aqds.c
> +++ b/board/freescale/ls1021aqds/ls1021aqds.c
> @@ -277,7 +277,7 @@ int board_early_init_f(void)
>   {
>   	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>   	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
> -	unsigned int major;
> +	unsigned int major, reg;
>
>   #ifdef CONFIG_TSEC_ENET
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> @@ -309,6 +309,17 @@ int board_early_init_f(void)
>   	out_be32(&scfg->eddrtqcfg, 0x63b20002);
>
>   	/*
> +	 * EDDRTQCFG Registers are Integration Strap values which controls
> +	 * performance parameters for DDR Controller.

   Would this comment not be better placed in your patch 1/2. Please
see my comments there.

> +	 * The bit 25(0x40) is used for disable priorities within DDR.
> +	 * This is a workaround because of the DDR are connected backwards
> +	 * on Rev2.0.
> +	 */
> +	reg = in_be32(&scfg->eddrtqcfg);
> +	reg |= 0x40;
> +	out_be32(&scfg->eddrtqcfg, reg);
> +
> +	/*
>   	 * Enable snoop requests and DVM message requests for
>   	 * Slave insterface S4 (A7 core cluster)
>   	 */
> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
> index c565e91..53bea95 100644
> --- a/board/freescale/ls1021atwr/ls1021atwr.c
> +++ b/board/freescale/ls1021atwr/ls1021atwr.c
> @@ -478,7 +478,7 @@ int board_early_init_f(void)
>   {
>   	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>   	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
> -	unsigned int major;
> +	unsigned int major, reg;
>
>   #ifdef CONFIG_TSEC_ENET
>   	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
> @@ -511,6 +511,17 @@ int board_early_init_f(void)
>   	out_be32(&scfg->eddrtqcfg, 0x63b20002);
>
>   	/*
> +	 * EDDRTQCFG Registers are Integration Strap values which controls
> +	 * performance parameters for DDR Controller.
> +	 * The bit 25(0x40) is used for disable priorities within DDR.
> +	 * This is a workaround because of the DDR are connected backwards
> +	 * on Rev2.0.
> +	 */
> +	reg = in_be32(&scfg->eddrtqcfg);
> +	reg |= 0x40;
> +	out_be32(&scfg->eddrtqcfg, reg);
> +
> +	/*
>   	 * Enable snoop requests and DVM message requests for
>   	 * Slave insterface S4 (A7 core cluster)
>   	 */
>

   Regards
   Sinan Akman