[U-Boot] [PATCH 0/4] arm: at91: change mpddr and support picosam9g45

[U-Boot] [PATCH 0/4] arm: at91: change mpddr and support picosam9g45

[Erik van Luijk]

This patchset adds support for the mini-box picosam9g45.
As this board uses both DDR controllers. The mpddr had to be patched to
be able to call ddr2_init() with a BASE register address parameter.

Erik van Luijk (4):
  arm: at91: mpddr: allow multiple DDR controllers
  arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init
  arm: at91: pmc: replace the constant with a define in at91_pmc.h
  arm: at91: add support for mini-box picosam9g45 board

 arch/arm/include/asm/mach-types.h               |   1 +
 arch/arm/mach-at91/Kconfig                      |   6 +
 arch/arm/mach-at91/include/mach/at91_pmc.h      |   1 +
 arch/arm/mach-at91/include/mach/atmel_mpddrc.h  |   6 +-
 arch/arm/mach-at91/mpddrc.c                     |  42 +--
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |  12 +-
 board/atmel/at91sam9n12ek/at91sam9n12ek.c       |   4 +-
 board/atmel/at91sam9x5ek/at91sam9x5ek.c         |   4 +-
 board/atmel/sama5d3_xplained/sama5d3_xplained.c |   4 +-
 board/atmel/sama5d3xek/sama5d3xek.c             |   4 +-
 board/atmel/sama5d4_xplained/sama5d4_xplained.c |   4 +-
 board/atmel/sama5d4ek/sama5d4ek.c               |   4 +-
 board/mini-box/picosam9g45/Kconfig              |  12 +
 board/mini-box/picosam9g45/MAINTAINERS          |   6 +
 board/mini-box/picosam9g45/Makefile             |  19 ++
 board/mini-box/picosam9g45/led.c                |  25 ++
 board/mini-box/picosam9g45/picosam9g45.c        | 354 ++++++++++++++++++++++++
 board/siemens/corvus/board.c                    |  12 +-
 configs/picosam9g45_defconfig                   |  12 +
 include/configs/at91sam9m10g45ek.h              |   1 -
 include/configs/at91sam9n12ek.h                 |   2 -
 include/configs/at91sam9x5ek.h                  |   2 -
 include/configs/corvus.h                        |   2 -
 include/configs/picosam9g45.h                   | 206 ++++++++++++++
 24 files changed, 685 insertions(+), 60 deletions(-)
 create mode 100644 board/mini-box/picosam9g45/Kconfig
 create mode 100644 board/mini-box/picosam9g45/MAINTAINERS
 create mode 100644 board/mini-box/picosam9g45/Makefile
 create mode 100644 board/mini-box/picosam9g45/led.c
 create mode 100644 board/mini-box/picosam9g45/picosam9g45.c
 create mode 100644 configs/picosam9g45_defconfig
 create mode 100644 include/configs/picosam9g45.h

-- 
1.9.1

[U-Boot] [PATCH 1/4] arm: at91: mpddr: allow multiple DDR controllers

[Erik van Luijk]

The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
---
 arch/arm/mach-at91/include/mach/atmel_mpddrc.h  |  6 ++--
 arch/arm/mach-at91/mpddrc.c                     | 42 ++++++++++++++-----------
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |  2 +-
 board/atmel/at91sam9n12ek/at91sam9n12ek.c       |  2 +-
 board/atmel/at91sam9x5ek/at91sam9x5ek.c         |  2 +-
 board/atmel/sama5d3_xplained/sama5d3_xplained.c |  2 +-
 board/atmel/sama5d3xek/sama5d3xek.c             |  2 +-
 board/atmel/sama5d4_xplained/sama5d4_xplained.c |  2 +-
 board/atmel/sama5d4ek/sama5d4ek.c               |  2 +-
 board/siemens/corvus/board.c                    |  2 +-
 include/configs/at91sam9m10g45ek.h              |  1 -
 include/configs/at91sam9n12ek.h                 |  2 --
 include/configs/at91sam9x5ek.h                  |  2 --
 include/configs/corvus.h                        |  2 --
 14 files changed, 35 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index 130a85a..c6c8dda 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -23,8 +23,10 @@ struct atmel_mpddr {
 	u32 md;
 };
 
-int ddr2_init(const unsigned int ram_address,
-	       const struct atmel_mpddr *mpddr);
+
+int ddr2_init(const unsigned int base,
+	      const unsigned int ram_address,
+	      const struct atmel_mpddr *mpddr);
 
 /* Bit field in mode register */
 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index e2b6a49..c085f8a 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -9,10 +9,10 @@
 #include <asm/io.h>
 #include <asm/arch/atmel_mpddrc.h>
 
-static inline void atmel_mpddr_op(int mode, u32 ram_address)
+static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
+	      int mode,
+	      u32 ram_address)
 {
-	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
-
 	writel(mode, &mpddr->mr);
 	writel(0, ram_address);
 }
@@ -27,10 +27,13 @@ static int ddr2_decodtype_is_seq(u32 cr)
 	return 1;
 }
 
-int ddr2_init(const unsigned int ram_address,
+
+int ddr2_init(const unsigned int base,
+	      const unsigned int ram_address,
 	      const struct atmel_mpddr *mpddr_value)
 {
-	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
+
 	u32 ba_off, cr;
 
 	/* Compute bank offset according to NC in configuration register */
@@ -52,30 +55,30 @@ int ddr2_init(const unsigned int ram_address,
 	writel(mpddr_value->tpr2, &mpddr->tpr2);
 
 	/* Issue a NOP command */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
 
 	/* A 200 us is provided to precede any signal toggle */
 	udelay(200);
 
 	/* Issue a NOP command */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
 
 	/* Issue an all banks precharge command */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
 
 	/* Issue an extended mode register set(EMRS2) to choose operation */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
 		       ram_address + (0x2 << ba_off));
 
 	/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
 		       ram_address + (0x3 << ba_off));
 
 	/*
 	 * Issue an extended mode register set(EMRS1) to enable DLL and
 	 * program D.I.C (output driver impedance control)
 	 */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
 		       ram_address + (0x1 << ba_off));
 
 	/* Enable DLL reset */
@@ -83,21 +86,21 @@ int ddr2_init(const unsigned int ram_address,
 	writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
 
 	/* A mode register set(MRS) cycle is issued to reset DLL */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
 
 	/* Issue an all banks precharge command */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
 
 	/* Two auto-refresh (CBR) cycles are provided */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
 
 	/* Disable DLL reset */
 	cr = readl(&mpddr->cr);
 	writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
 
 	/* A mode register set (MRS) cycle is issued to disable DLL reset */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
 
 	/* Set OCD calibration in default state */
 	cr = readl(&mpddr->cr);
@@ -107,7 +110,7 @@ int ddr2_init(const unsigned int ram_address,
 	 * An extended mode register set (EMRS1) cycle is issued
 	 * to OCD default value
 	 */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
 		       ram_address + (0x1 << ba_off));
 
 	 /* OCD calibration mode exit */
@@ -118,11 +121,11 @@ int ddr2_init(const unsigned int ram_address,
 	 * An extended mode register set (EMRS1) cycle is issued
 	 * to enable OCD exit
 	 */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
 		       ram_address + (0x1 << ba_off));
 
 	/* A nornal mode command is provided */
-	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
 
 	/* Perform a write access to any DDR2-SDRAM address */
 	writel(0, ram_address);
@@ -132,3 +135,4 @@ int ddr2_init(const unsigned int ram_address,
 
 	return 0;
 }
+
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 4289179..3e65d71 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -147,7 +147,7 @@ void mem_init(void)
 	writel(csa, &mat->ebicsa);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_CS6, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 }
 #endif
 
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 4f46a03..8437f37 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -327,6 +327,6 @@ void mem_init(void)
 	writel(csa, &matrix->ebicsa);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_CS1, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 }
 #endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 114ac5c..0455e2c 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -364,6 +364,6 @@ void mem_init(void)
 	writel(csa, &matrix->ebicsa);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_CS1, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 }
 #endif
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 92ed4e8..0793e4a 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -194,7 +194,7 @@ void mem_init(void)
 	writel(0x4, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
 
 void at91_pmc_init(void)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index cf6ed8b..d6e7e16 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -433,7 +433,7 @@ void mem_init(void)
 	writel(0x4, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
 
 void at91_pmc_init(void)
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 7d447fe..71ec4b7 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -393,7 +393,7 @@ void mem_init(void)
 	writel(0x4, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
 
 void at91_pmc_init(void)
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index e9bbb4b..de4291f 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -389,7 +389,7 @@ void mem_init(void)
 	writel(0x4, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
 
 void at91_pmc_init(void)
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index f3f6dae..9001fcbcf 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -160,7 +160,7 @@ void mem_init(void)
 	writel(csa, &mat->ebicsa);
 
 	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_CS6, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 }
 #endif
 
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 09d8bec..26edab8 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -252,5 +252,4 @@
 #define CONFIG_SYS_MCKR			0x1301
 #define CONFIG_SYS_MCKR_CSS		0x1302
 
-#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC0
 #endif
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index a19d4d9..6b00c6a 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -260,8 +260,6 @@
 #define CONFIG_SYS_MCKR			0x1301
 #define CONFIG_SYS_MCKR_CSS		0x1302
 
-#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC
-
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
 #define CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index b9a7754..b94f5ac 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -262,8 +262,6 @@
 #define CONFIG_SYS_MCKR			0x1301
 #define CONFIG_SYS_MCKR_CSS		0x1302
 
-#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC
-
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
 #define CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 3cfae21..4069082 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -194,6 +194,4 @@
 #define CONFIG_SYS_MCKR			0x1301
 #define CONFIG_SYS_MCKR_CSS		0x1302
 
-#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC0
-
 #endif
-- 
1.9.1

[U-Boot] [PATCH 2/4] arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init

[Erik van Luijk]

On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
---
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 8 --------
 board/siemens/corvus/board.c                    | 8 --------
 2 files changed, 16 deletions(-)

diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 3e65d71..d2ade4d 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -131,21 +131,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
 void mem_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 	struct atmel_mpddr ddr2;
-	unsigned long csa;
 
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
 	writel(0x4, &pmc->scer);
 
-	/* Chip select 1 is for DDR2/SDRAM */
-	csa = readl(&mat->ebicsa);
-	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
-	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
-	writel(csa, &mat->ebicsa);
-
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 }
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index 9001fcbcf..d74743f 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -144,21 +144,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
 void mem_init(void)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 	struct atmel_mpddr ddr2;
-	unsigned long csa;
 
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
 	writel(0x4, &pmc->scer);
 
-	/* Chip select 1 is for DDR2/SDRAM */
-	csa = readl(&mat->ebicsa);
-	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
-	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
-	writel(csa, &mat->ebicsa);
-
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
 }
-- 
1.9.1

[U-Boot] [PATCH 3/4] arm: at91: pmc: replace the constant with a define in at91_pmc.h

[Erik van Luijk]

To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 <<  2).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
---
 arch/arm/mach-at91/include/mach/at91_pmc.h      | 1 +
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +-
 board/atmel/at91sam9n12ek/at91sam9n12ek.c       | 2 +-
 board/atmel/at91sam9x5ek/at91sam9x5ek.c         | 2 +-
 board/atmel/sama5d3_xplained/sama5d3_xplained.c | 2 +-
 board/atmel/sama5d3xek/sama5d3xek.c             | 2 +-
 board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +-
 board/atmel/sama5d4ek/sama5d4ek.c               | 2 +-
 board/siemens/corvus/board.c                    | 2 +-
 9 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index ebb7dec..8a3fb94 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -158,6 +158,7 @@ typedef struct at91_pmc {
 
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
+#define		AT91_PMC_DDR		(1 <<  2)		/* DDR Clock */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
 #define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index d2ade4d..2fea56f 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -136,7 +136,7 @@ void mem_init(void)
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index 8437f37..59bc535 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -316,7 +316,7 @@ void mem_init(void)
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* Chip select 1 is for DDR2/SDRAM */
 	csa = readl(&matrix->ebicsa);
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 0455e2c..1738a2b 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -353,7 +353,7 @@ void mem_init(void)
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* Chip select 1 is for DDR2/SDRAM */
 	csa = readl(&matrix->ebicsa);
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 0793e4a..7a01149 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -191,7 +191,7 @@ void mem_init(void)
 
 	/* enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index d6e7e16..2bd436a 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -430,7 +430,7 @@ void mem_init(void)
 
 	/* enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 71ec4b7..db45331 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -390,7 +390,7 @@ void mem_init(void)
 
 	/* enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index de4291f..357b223 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -386,7 +386,7 @@ void mem_init(void)
 
 	/* enable MPDDR clock */
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index d74743f..3294203 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -149,7 +149,7 @@ void mem_init(void)
 	ddr2_conf(&ddr2);
 
 	/* enable DDR2 clock */
-	writel(0x4, &pmc->scer);
+	writel(AT91_PMC_DDR, &pmc->scer);
 
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
-- 
1.9.1

[U-Boot] [PATCH 4/4] arm: at91: add support for mini-box picosam9g45 board

[Erik van Luijk]

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
---
 arch/arm/include/asm/mach-types.h        |   1 +
 arch/arm/mach-at91/Kconfig               |   6 +
 board/mini-box/picosam9g45/Kconfig       |  12 ++
 board/mini-box/picosam9g45/MAINTAINERS   |   6 +
 board/mini-box/picosam9g45/Makefile      |  19 ++
 board/mini-box/picosam9g45/led.c         |  25 +++
 board/mini-box/picosam9g45/picosam9g45.c | 354 +++++++++++++++++++++++++++++++
 configs/picosam9g45_defconfig            |  12 ++
 include/configs/picosam9g45.h            | 206 ++++++++++++++++++
 9 files changed, 641 insertions(+)
 create mode 100644 board/mini-box/picosam9g45/Kconfig
 create mode 100644 board/mini-box/picosam9g45/MAINTAINERS
 create mode 100644 board/mini-box/picosam9g45/Makefile
 create mode 100644 board/mini-box/picosam9g45/led.c
 create mode 100644 board/mini-box/picosam9g45/picosam9g45.c
 create mode 100644 configs/picosam9g45_defconfig
 create mode 100644 include/configs/picosam9g45.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 5afe791..912cb90 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_PICOSAM9G45          3838
 #define MACH_TYPE_ARMADILLO_800EVA     3863
 #define MACH_TYPE_KZM9G                4140
 #define MACH_TYPE_COLIBRI_T30          4493
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bbf4228..423be56 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -64,6 +64,11 @@ config TARGET_PM9G45
 	bool "Ronetix pm9g45 board"
 	select CPU_ARM926EJS
 
+config TARGET_PICOSAM9G45
+	bool "Mini-box picosam9g45 board"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config TARGET_AT91SAM9N12EK
 	bool "Atmel AT91SAM9N12-EK board"
 	select CPU_ARM926EJS
@@ -150,6 +155,7 @@ source "board/egnite/ethernut5/Kconfig"
 source "board/esd/meesc/Kconfig"
 source "board/esd/otc570/Kconfig"
 source "board/eukrea/cpu9260/Kconfig"
+source "board/mini-box/picosam9g45/Kconfig"
 source "board/ronetix/pm9261/Kconfig"
 source "board/ronetix/pm9263/Kconfig"
 source "board/ronetix/pm9g45/Kconfig"
diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig
new file mode 100644
index 0000000..98ec0c4
--- /dev/null
+++ b/board/mini-box/picosam9g45/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PICOSAM9G45
+
+config SYS_BOARD
+	default "picosam9g45"
+
+config SYS_VENDOR
+	default "mini-box"
+
+config SYS_CONFIG_NAME
+	default "picosam9g45"
+
+endif
diff --git a/board/mini-box/picosam9g45/MAINTAINERS b/board/mini-box/picosam9g45/MAINTAINERS
new file mode 100644
index 0000000..3e3e2a9
--- /dev/null
+++ b/board/mini-box/picosam9g45/MAINTAINERS
@@ -0,0 +1,6 @@
+PICOSAM9G45 BOARD
+M:	Erik van Luijk <evanluijk@interact.nl>
+S:	Maintained
+F:	board/mini-box/picosam9g45/
+F:	include/configs/picosam9g45.h
+F:	configs/picosam9g45_mmc_defconfig
diff --git a/board/mini-box/picosam9g45/Makefile b/board/mini-box/picosam9g45/Makefile
new file mode 100644
index 0000000..bf6e8e3
--- /dev/null
+++ b/board/mini-box/picosam9g45/Makefile
@@ -0,0 +1,19 @@
+#
+# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+# (C) Copytight 2015 Inter Act B.V.
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += picosam9g45.o
+obj-y += led.o
diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c
new file mode 100644
index 0000000..dc1013a
--- /dev/null
+++ b/board/mini-box/picosam9g45/led.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c
new file mode 100644
index 0000000..eb0f2dd
--- /dev/null
+++ b/board/mini-box/picosam9g45/picosam9g45.c
@@ -0,0 +1,354 @@
+/*
+ * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/mtd/nand.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void picosam9g45_usb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void picosam9g45_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void picosam9g45_lcd_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("(C) 2015 Inter Act B.V.\n");
+	lcd_printf("support at interact.nl\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		   ARMEL_CPU_NAME,
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+	picosam9g45_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+	picosam9g45_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	picosam9g45_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+							PHYS_SDRAM_2_SIZE);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 0);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 1);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 1);
+	break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
new file mode 100644
index 0000000..4128193
--- /dev/null
+++ b/configs/picosam9g45_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_PICOSAM9G45=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
new file mode 100644
index 0000000..feac8ad
--- /dev/null
+++ b/include/configs/picosam9g45.h
@@ -0,0 +1,206 @@
+/*
+ * Configuration settings for the mini-box PICOSAM9G45 board.
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_PICOSAM
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x23E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		ATMEL_BASE_CS1	/* on DDRSDRC1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_2		ATMEL_BASE_CS6	/* on DDRSDRC0 */
+#define PHYS_SDRAM_2_SIZE       0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env + linux in mmc */
+#define FAT_ENV_INTERFACE	"mmc"
+/*
+ * We don't specify the part number, if device 0 has partition table, it means
+ * the first partition; it no partition table, then take whole device as a
+ * FAT file system.
+ */
+#define FAT_ENV_DEVICE_AND_PART	"0"
+#define FAT_ENV_FILE		"uboot.env"
+#define CONFIG_ENV_IS_IN_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mmcblk0p2 rw rootwait"
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE  \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SPL_LDSCRIPT	arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
+#endif
-- 
1.9.1

[U-Boot] [PATCH v2 4/4] arm: at91: add support for mini-box picosam9g45 board

[Erik van Luijk]

Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)

CPU: AT91SAM9G45
Crystal frequency:       12 MHz
CPU clock        :      400 MHz
Master clock     :  133.333 MHz
       Watchdog enabled
DRAM:  256 MiB
WARNING: Caches not enabled
MMC:   mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Error: macb0 address not set.

Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
---

Changes in v2:
- Enable watchdog
- Fix typo in lcd_show_board_info()

 arch/arm/include/asm/mach-types.h        |   1 +
 arch/arm/mach-at91/Kconfig               |   6 +
 board/mini-box/picosam9g45/Kconfig       |  12 ++
 board/mini-box/picosam9g45/MAINTAINERS   |   6 +
 board/mini-box/picosam9g45/Makefile      |  19 ++
 board/mini-box/picosam9g45/led.c         |  25 +++
 board/mini-box/picosam9g45/picosam9g45.c | 354 +++++++++++++++++++++++++++++++
 configs/picosam9g45_defconfig            |  12 ++
 include/configs/picosam9g45.h            | 211 ++++++++++++++++++
 9 files changed, 646 insertions(+)
 create mode 100644 board/mini-box/picosam9g45/Kconfig
 create mode 100644 board/mini-box/picosam9g45/MAINTAINERS
 create mode 100644 board/mini-box/picosam9g45/Makefile
 create mode 100644 board/mini-box/picosam9g45/led.c
 create mode 100644 board/mini-box/picosam9g45/picosam9g45.c
 create mode 100644 configs/picosam9g45_defconfig
 create mode 100644 include/configs/picosam9g45.h

diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 5afe791..912cb90 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_PICOSAM9G45          3838
 #define MACH_TYPE_ARMADILLO_800EVA     3863
 #define MACH_TYPE_KZM9G                4140
 #define MACH_TYPE_COLIBRI_T30          4493
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index bbf4228..423be56 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -64,6 +64,11 @@ config TARGET_PM9G45
 	bool "Ronetix pm9g45 board"
 	select CPU_ARM926EJS
 
+config TARGET_PICOSAM9G45
+	bool "Mini-box picosam9g45 board"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config TARGET_AT91SAM9N12EK
 	bool "Atmel AT91SAM9N12-EK board"
 	select CPU_ARM926EJS
@@ -150,6 +155,7 @@ source "board/egnite/ethernut5/Kconfig"
 source "board/esd/meesc/Kconfig"
 source "board/esd/otc570/Kconfig"
 source "board/eukrea/cpu9260/Kconfig"
+source "board/mini-box/picosam9g45/Kconfig"
 source "board/ronetix/pm9261/Kconfig"
 source "board/ronetix/pm9263/Kconfig"
 source "board/ronetix/pm9g45/Kconfig"
diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig
new file mode 100644
index 0000000..98ec0c4
--- /dev/null
+++ b/board/mini-box/picosam9g45/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_PICOSAM9G45
+
+config SYS_BOARD
+	default "picosam9g45"
+
+config SYS_VENDOR
+	default "mini-box"
+
+config SYS_CONFIG_NAME
+	default "picosam9g45"
+
+endif
diff --git a/board/mini-box/picosam9g45/MAINTAINERS b/board/mini-box/picosam9g45/MAINTAINERS
new file mode 100644
index 0000000..3e3e2a9
--- /dev/null
+++ b/board/mini-box/picosam9g45/MAINTAINERS
@@ -0,0 +1,6 @@
+PICOSAM9G45 BOARD
+M:	Erik van Luijk <evanluijk@interact.nl>
+S:	Maintained
+F:	board/mini-box/picosam9g45/
+F:	include/configs/picosam9g45.h
+F:	configs/picosam9g45_mmc_defconfig
diff --git a/board/mini-box/picosam9g45/Makefile b/board/mini-box/picosam9g45/Makefile
new file mode 100644
index 0000000..bf6e8e3
--- /dev/null
+++ b/board/mini-box/picosam9g45/Makefile
@@ -0,0 +1,19 @@
+#
+# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+# (C) Copytight 2015 Inter Act B.V.
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += picosam9g45.o
+obj-y += led.o
diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c
new file mode 100644
index 0000000..dc1013a
--- /dev/null
+++ b/board/mini-box/picosam9g45/led.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c
new file mode 100644
index 0000000..afbd6ce
--- /dev/null
+++ b/board/mini-box/picosam9g45/picosam9g45.c
@@ -0,0 +1,354 @@
+/*
+ * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/mtd/nand.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void picosam9g45_usb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void picosam9g45_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void picosam9g45_lcd_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("(C) 2015 Inter Act B.V.\n");
+	lcd_printf("support at interact.nl\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		   ATMEL_CPU_NAME,
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+	picosam9g45_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+	picosam9g45_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	picosam9g45_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+							PHYS_SDRAM_2_SIZE);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 0);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 1);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 1);
+	break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
new file mode 100644
index 0000000..4128193
--- /dev/null
+++ b/configs/picosam9g45_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_PICOSAM9G45=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
new file mode 100644
index 0000000..e3039c2
--- /dev/null
+++ b/include/configs/picosam9g45.h
@@ -0,0 +1,211 @@
+/*
+ * Configuration settings for the mini-box PICOSAM9G45 board.
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_PICOSAM
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x23E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Enable the watchdog */
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Command line configuration.
+ */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		ATMEL_BASE_CS1	/* on DDRSDRC1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_2		ATMEL_BASE_CS6	/* on DDRSDRC0 */
+#define PHYS_SDRAM_2_SIZE       0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env + linux in mmc */
+#define FAT_ENV_INTERFACE	"mmc"
+/*
+ * We don't specify the part number, if device 0 has partition table, it means
+ * the first partition; it no partition table, then take whole device as a
+ * FAT file system.
+ */
+#define FAT_ENV_DEVICE_AND_PART	"0"
+#define FAT_ENV_FILE		"uboot.env"
+#define CONFIG_ENV_IS_IN_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mmcblk0p2 rw rootwait"
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE  \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SPL_LDSCRIPT	arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
+#endif
-- 
1.9.1

[U-Boot] [PATCH 2/4] arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init

[Andreas Bießmann]

Hi Erik,

On 08/13/2015 03:43 PM, Erik van Luijk wrote:
> On these boards the DDR is connected to a dedicated controller and not
> to chip select 1 of the EBI.

from the specs this seems correct. Could I please get a Tested-by, since
I do not own one of these boards.

Best regards

Andreas

> 
> Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
> ---
>  board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 8 --------
>  board/siemens/corvus/board.c                    | 8 --------
>  2 files changed, 16 deletions(-)
> 
> diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
> index 3e65d71..d2ade4d 100644
> --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
> +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
> @@ -131,21 +131,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
>  void mem_init(void)
>  {
>  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> -	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
>  	struct atmel_mpddr ddr2;
> -	unsigned long csa;
>  
>  	ddr2_conf(&ddr2);
>  
>  	/* enable DDR2 clock */
>  	writel(0x4, &pmc->scer);
>  
> -	/* Chip select 1 is for DDR2/SDRAM */
> -	csa = readl(&mat->ebicsa);
> -	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
> -	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
> -	writel(csa, &mat->ebicsa);
> -
>  	/* DDRAM2 Controller initialize */
>  	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
>  }
> diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
> index 9001fcbcf..d74743f 100644
> --- a/board/siemens/corvus/board.c
> +++ b/board/siemens/corvus/board.c
> @@ -144,21 +144,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
>  void mem_init(void)
>  {
>  	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
> -	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
>  	struct atmel_mpddr ddr2;
> -	unsigned long csa;
>  
>  	ddr2_conf(&ddr2);
>  
>  	/* enable DDR2 clock */
>  	writel(0x4, &pmc->scer);
>  
> -	/* Chip select 1 is for DDR2/SDRAM */
> -	csa = readl(&mat->ebicsa);
> -	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
> -	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
> -	writel(csa, &mat->ebicsa);
> -
>  	/* DDRAM2 Controller initialize */
>  	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
>  }
> 

[U-Boot] [PATCH 3/4] arm: at91: pmc: replace the constant with a define in at91_pmc.h

[Andreas Bießmann]

On 08/13/2015 03:43 PM, Erik van Luijk wrote:
> To enable the clocks on the at91 boards a constant (0x4) is used.
> This is replaced with a define in at91_pmc.h (1 <<  2).
> 
> Signed-off-by: Erik van Luijk <evanluijk@interact.nl>

Reviewed-by: Andreas Bie?mann <andreas.devel@gmail.com>

> ---
>  arch/arm/mach-at91/include/mach/at91_pmc.h      | 1 +
>  board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +-
>  board/atmel/at91sam9n12ek/at91sam9n12ek.c       | 2 +-
>  board/atmel/at91sam9x5ek/at91sam9x5ek.c         | 2 +-
>  board/atmel/sama5d3_xplained/sama5d3_xplained.c | 2 +-
>  board/atmel/sama5d3xek/sama5d3xek.c             | 2 +-
>  board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +-
>  board/atmel/sama5d4ek/sama5d4ek.c               | 2 +-
>  board/siemens/corvus/board.c                    | 2 +-
>  9 files changed, 9 insertions(+), 8 deletions(-)

[U-Boot] [PATCH 2/4] arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init

[Erik van Luijk]

Hi Andreas,

I tested this commit on my picosam9g45, the design of the primary DDR 
controller is equal to the at91sam9m10g45ek board.

0x20000000 is the memory at CS1 (not initialized/available)
0x70000000 is the memory at the primary DDR controller (should work)

On the picosam9g45 there is no NAND flash. When NAND /and/ DDR were 
connected to the EBI the EBISHARE at DDRSDRC_CR bit had to be enabled.

Bootlog:
U-Boot SPL 2015.10-rc1-00450-gac60584 (Aug 18 2015 - 11:56:48)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img


U-Boot 2015.10-rc1-00450-gac60584 (Aug 18 2015 - 11:56:48 +0000)

CPU: AT91SAM9G45
Crystal frequency:       12 MHz
CPU clock        :      400 MHz
Master clock     :  133.333 MHz
DRAM:  128 MiB
WARNING: Caches not enabled
NAND:  atmel_nand: Fail to initialize #0 chip0 MiB
MMC:   mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Error: macb0 address not set.

Hit any key to stop autoboot:  0
U-Boot> mw 0x20000000 deadbeef 3
U-Boot> md 0x20000000 4
20000000: ffffffff ffffffff ffffffff ffffffff    ................
U-Boot> mw 0x70000000 12c0ffee 3
U-Boot> md 0x70000000 4
70000000: 12c0ffee 12c0ffee 12c0ffee 73f00000    ...............s
U-Boot>


Andreas Bie?mann schreef op 18-8-2015 om 12:30:
> Hi Erik,
>
> On 08/13/2015 03:43 PM, Erik van Luijk wrote:
>> On these boards the DDR is connected to a dedicated controller and not
>> to chip select 1 of the EBI.
>
> from the specs this seems correct. Could I please get a Tested-by, since
> I do not own one of these boards.

Tested-by: Erik van Luijk <evanluijk@interact.nl>

>
> Best regards
>
> Andreas

Regards Erik.
>
>>
>> Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
>> ---
>>   board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 8 --------
>>   board/siemens/corvus/board.c                    | 8 --------
>>   2 files changed, 16 deletions(-)
>>
>> diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
>> index 3e65d71..d2ade4d 100644
>> --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
>> +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
>> @@ -131,21 +131,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
>>   void mem_init(void)
>>   {
>>   	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>> -	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
>>   	struct atmel_mpddr ddr2;
>> -	unsigned long csa;
>>
>>   	ddr2_conf(&ddr2);
>>
>>   	/* enable DDR2 clock */
>>   	writel(0x4, &pmc->scer);
>>
>> -	/* Chip select 1 is for DDR2/SDRAM */
>> -	csa = readl(&mat->ebicsa);
>> -	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
>> -	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
>> -	writel(csa, &mat->ebicsa);
>> -
>>   	/* DDRAM2 Controller initialize */
>>   	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
>>   }
>> diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
>> index 9001fcbcf..d74743f 100644
>> --- a/board/siemens/corvus/board.c
>> +++ b/board/siemens/corvus/board.c
>> @@ -144,21 +144,13 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
>>   void mem_init(void)
>>   {
>>   	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
>> -	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
>>   	struct atmel_mpddr ddr2;
>> -	unsigned long csa;
>>
>>   	ddr2_conf(&ddr2);
>>
>>   	/* enable DDR2 clock */
>>   	writel(0x4, &pmc->scer);
>>
>> -	/* Chip select 1 is for DDR2/SDRAM */
>> -	csa = readl(&mat->ebicsa);
>> -	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
>> -	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
>> -	writel(csa, &mat->ebicsa);
>> -
>>   	/* DDRAM2 Controller initialize */
>>   	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
>>   }
>>
>

[U-Boot] [U-Boot, 1/4] arm: at91: mpddr: allow multiple DDR controllers

[Andreas Bießmann]

Dear Erik van Luijk,

Erik van Luijk <evanluijk@interact.nl> writes:
>The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
>This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).
>
>Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
>[remove 'new blank line at EOF']
>Signed-off-by: Andreas Bie?mann <andreas.devel@googlemail.com>
>---
> arch/arm/mach-at91/include/mach/atmel_mpddrc.h  |  6 ++--
> arch/arm/mach-at91/mpddrc.c                     | 42 ++++++++++++++-----------
> board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |  2 +-
> board/atmel/at91sam9n12ek/at91sam9n12ek.c       |  2 +-
> board/atmel/at91sam9x5ek/at91sam9x5ek.c         |  2 +-
> board/atmel/sama5d3_xplained/sama5d3_xplained.c |  2 +-
> board/atmel/sama5d3xek/sama5d3xek.c             |  2 +-
> board/atmel/sama5d4_xplained/sama5d4_xplained.c |  2 +-
> board/atmel/sama5d4ek/sama5d4ek.c               |  2 +-
> board/siemens/corvus/board.c                    |  2 +-
> include/configs/at91sam9m10g45ek.h              |  1 -
> include/configs/at91sam9n12ek.h                 |  2 --
> include/configs/at91sam9x5ek.h                  |  2 --
> include/configs/corvus.h                        |  2 --
> 14 files changed, 35 insertions(+), 36 deletions(-)

applied to u-boot-atmel/master, thanks!

Fixed patch while applying and removed one empty
 line at EOF.

Best regards,
Andreas Bie?mann

[U-Boot] [U-Boot, 2/4] arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init

[Andreas Bießmann]

Dear Erik van Luijk,

Erik van Luijk <evanluijk@interact.nl> writes:
>On these boards the DDR is connected to a dedicated controller and not
>to chip select 1 of the EBI.
>
>Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
>Tested-by: Erik van Luijk <evanluijk@interact.nl>
>---
> board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 8 --------
> board/siemens/corvus/board.c                    | 8 --------
> 2 files changed, 16 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bie?mann

[U-Boot] [U-Boot, 3/4] arm: at91: pmc: replace the constant with a define in at91_pmc.h

[Andreas Bießmann]

Dear Erik van Luijk,

Erik van Luijk <evanluijk@interact.nl> writes:
>To enable the clocks on the at91 boards a constant (0x4) is used.
>This is replaced with a define in at91_pmc.h (1 <<  2).
>
>Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
>Reviewed-by: Andreas Bie?mann <andreas.devel@googlemail.com>
>---
> arch/arm/mach-at91/include/mach/at91_pmc.h      | 1 +
> board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 2 +-
> board/atmel/at91sam9n12ek/at91sam9n12ek.c       | 2 +-
> board/atmel/at91sam9x5ek/at91sam9x5ek.c         | 2 +-
> board/atmel/sama5d3_xplained/sama5d3_xplained.c | 2 +-
> board/atmel/sama5d3xek/sama5d3xek.c             | 2 +-
> board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 +-
> board/atmel/sama5d4ek/sama5d4ek.c               | 2 +-
> board/siemens/corvus/board.c                    | 2 +-
> 9 files changed, 9 insertions(+), 8 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bie?mann

[U-Boot] [U-Boot, v2, 4/4] arm: at91: add support for mini-box picosam9g45 board

[Andreas Bießmann]

Dear Erik van Luijk,

Erik van Luijk <evanluijk@interact.nl> writes:
>Bootlog:
>U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
>mci: setting clock 258000 Hz, block size 512
>mci: setting clock 258000 Hz, block size 512
>mci: setting clock 258000 Hz, block size 512
>mci: setting clock 33024000 Hz, block size 512
>reading u-boot.img
>reading u-boot.img
>
>U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)
>
>CPU: AT91SAM9G45
>Crystal frequency:       12 MHz
>CPU clock        :      400 MHz
>Master clock     :  133.333 MHz
>       Watchdog enabled
>DRAM:  256 MiB
>WARNING: Caches not enabled
>MMC:   mci: 0
>mci: setting clock 260416 Hz, block size 512
>mci: setting clock 260416 Hz, block size 512
>mci: setting clock 260416 Hz, block size 512
>mci: setting clock 33333333 Hz, block size 512
>reading uboot.env
>In:    serial
>Out:   serial
>Err:   serial
>Net:   macb0
>Error: macb0 address not set.
>
>Hit any key to stop autoboot:  0
>U-Boot>
>
>Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
>[add 'picosam9g45_defconfig' to MAINTAINERS]
>Signed-off-by: Andreas Bie?mann <andreas.devel@googlemail.com>
>---
>
>Changes in v2:
>- Enable watchdog
>- Fix typo in lcd_show_board_info()
>
> arch/arm/include/asm/mach-types.h        |   1 +
> arch/arm/mach-at91/Kconfig               |   6 +
> board/mini-box/picosam9g45/Kconfig       |  12 ++
> board/mini-box/picosam9g45/MAINTAINERS   |   6 +
> board/mini-box/picosam9g45/Makefile      |  19 ++
> board/mini-box/picosam9g45/led.c         |  25 +++
> board/mini-box/picosam9g45/picosam9g45.c | 354 +++++++++++++++++++++++++++++++
> configs/picosam9g45_defconfig            |  12 ++
> include/configs/picosam9g45.h            | 211 ++++++++++++++++++
> 9 files changed, 646 insertions(+)
> create mode 100644 board/mini-box/picosam9g45/Kconfig
> create mode 100644 board/mini-box/picosam9g45/MAINTAINERS
> create mode 100644 board/mini-box/picosam9g45/Makefile
> create mode 100644 board/mini-box/picosam9g45/led.c
> create mode 100644 board/mini-box/picosam9g45/picosam9g45.c
> create mode 100644 configs/picosam9g45_defconfig
> create mode 100644 include/configs/picosam9g45.h

applied to u-boot-atmel/master, thanks!

Fixed patch while applying and added one missing
 file to MAINTAINERS.

Best regards,
Andreas Bie?mann