From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Tue, 18 Aug 2015 12:13:27 -0700 Subject: [U-Boot] [PATCH 2/3] LS102XA:workaround:disable priorities within DDR In-Reply-To: <1439535264-41637-2-git-send-email-yao.yuan@freescale.com> References: <1439535264-41637-1-git-send-email-yao.yuan@freescale.com> <1439535264-41637-2-git-send-email-yao.yuan@freescale.com> Message-ID: <55D383D7.70009@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 08/13/2015 11:54 PM, Yuan Yao wrote: > EDDRTQCFG Registers are Integration Strap values which controls > performance parameters for DDR Controller. > > The bit 25 is used to disable priorities within DDR since DDR > are connected backwards on silicon Rev2.0. > > Signed-off-by: Yuan Yao > --- > board/freescale/ls1021aqds/ls1021aqds.c | 13 ++++++++++++- > board/freescale/ls1021atwr/ls1021atwr.c | 13 ++++++++++++- > 2 files changed, 24 insertions(+), 2 deletions(-) Yuan, SoC erratum workaround shouldn't be put into board file. York