From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Tue, 18 Aug 2015 15:27:29 -0500 Subject: [U-Boot] [PATCH] arm: socfpga: Fix delay in freeze controller In-Reply-To: <1439247603-8990-1-git-send-email-marex@denx.de> References: <1439247603-8990-1-git-send-email-marex@denx.de> Message-ID: <55D39531.4050701@opensource.altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 8/10/15 6:00 PM, Marek Vasut wrote: > Based on observation, this udelay(20) was apparently too high and caused > subsequent failure to calibrate DDR when U-Boot was compiled with certain > toolchains. Lowering this delay fixed the problem. > > Instead of permanently lowering the delay, calculate the correct delay > based on the original comment, that is, obtain EOSC1 frequency and use > it to calculate the precise delay. > > Signed-off-by: Marek Vasut > --- > arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c > index 0be643c..2b16795 100644 > --- a/arch/arm/mach-socfpga/freeze_controller.c > +++ b/arch/arm/mach-socfpga/freeze_controller.c > @@ -7,8 +7,8 @@ > Acked-by: Dinh Nguyen Thanks, Dinh