From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Thu, 20 Aug 2015 08:58:41 -0600 Subject: [U-Boot] [PATCH 2/6] ARM: tegra: Implement clk_m In-Reply-To: <1440063743-22838-2-git-send-email-thierry.reding@gmail.com> References: <1440063743-22838-1-git-send-email-thierry.reding@gmail.com> <1440063743-22838-2-git-send-email-thierry.reding@gmail.com> Message-ID: <55D5EB21.4030707@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 08/20/2015 03:42 AM, Thierry Reding wrote: > From: Thierry Reding > > On currently supported SoCs, clk_m always runs at the same frequency as > the oscillator input. However newer SoC generations such as Tegra210 no > longer have that restriction. Prepare for that by separating clk_m from > the oscillator clock and allow SoC code to override the clk_m rate. > diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h > index d8fa0e1d2cee..3f910f5ae8b9 100644 > --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h > +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h > @@ -38,6 +38,7 @@ enum clock_id { > /* These are the base clocks (inputs to the Tegra SOC) */ > CLOCK_ID_32KHZ, > CLOCK_ID_OSC, > + CLOCK_ID_CLK_M, > > CLOCK_ID_COUNT, /* number of PLLs */ > CLOCK_ID_DISPLAY2, /* placeholder */ clock.h contains the following: /* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) ... which would need to be updated. Related, see internal bug number 1676978 to see if any of the other gotchas there affect this patch.