From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration
Date: Thu, 20 Aug 2015 13:59:21 -0600 [thread overview]
Message-ID: <55D63199.8020708@wwwdotorg.org> (raw)
In-Reply-To: <1440057163-20081-1-git-send-email-marcel.ziswiler@toradex.com>
On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
>
> Implement early TPS6586X PMIC rail configuration setting SM0 being
> VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
>
> While those are PMIC power-up defaults the SoC might have been reset
> separately with certain rails being left at lower DVFS states which
> is e.g. the case upon watchdog reset while otherwise nearly idling.
Is there any guarantee that the voltage levels are high enough for the
AVP to run correctly before the CORE rail is adjusted? It sounds to me
like a HW design issue; the SoC reset output should reset the PMIC too.
next prev parent reply other threads:[~2015-08-20 19:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-20 7:52 [U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration Marcel Ziswiler
2015-08-20 7:52 ` [U-Boot] [PATCH 1/3] arm: tegra20: implement " Marcel Ziswiler
2015-08-20 20:01 ` Stephen Warren
2015-08-20 7:52 ` [U-Boot] [PATCH 2/3] colibri_t20: enable " Marcel Ziswiler
2015-08-20 20:02 ` Stephen Warren
2015-08-20 7:52 ` [U-Boot] [PATCH 3/3] colibri_t20: get rid of spurious MAX_I2C_RETRY define Marcel Ziswiler
2015-08-20 19:59 ` Stephen Warren [this message]
-- strict thread matches above, loose matches on Subject: below --
2015-08-20 22:59 [U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration Marcel Ziswiler
2015-08-24 16:26 ` Stephen Warren
2015-08-24 22:19 Marcel Ziswiler
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