[U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL

[Stefano Babic <sbabic@denx.de>]

On 12/08/2015 11:40, Peng Fan wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX6UL. Accessing these register will cause enet not work well.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> 
> Changes v2:
>  Using runtime check, but not hardcoding "#ifdef".
>  This patch depends on the runtime checking patch:
>  https://patchwork.ozlabs.org/patch/505621/.
> 
>  drivers/net/fec_mxc.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index c5dcbbb..bff5fd1 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -17,6 +17,7 @@
>  
>  #include <asm/arch/clock.h>
>  #include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/sys_proto.h>
>  #include <asm/io.h>
>  #include <asm/errno.h>
>  #include <linux/compiler.h>
> @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
>  	writel(0x00000000, &fec->eth->gaddr2);
>  
>  
> -	/* clear MIB RAM */
> -	for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> -		writel(0, i);
> +	/* Do not access reserved register for i.MX6UL */
> +	if (!is_cpu_type(MXC_CPU_MX6UL)) {
> +		/* clear MIB RAM */
> +		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> +			writel(0, i);
>  
> -	/* FIFO receive start register */
> -	writel(0x520, &fec->eth->r_fstart);
> +		/* FIFO receive start register */
> +		writel(0x520, &fec->eth->r_fstart);
> +	}
>  
>  	/* size and address of each buffer */
>  	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

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