From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 23 Aug 2015 18:42:04 +0200 Subject: [U-Boot] [PATCH v5 07/13] imx: imx7d: initial arch level support In-Reply-To: <1439310001-5643-7-git-send-email-aalonso@freescale.com> References: <1439310001-5643-1-git-send-email-aalonso@freescale.com> <1439310001-5643-7-git-send-email-aalonso@freescale.com> Message-ID: <55D9F7DC.4010106@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Adrian, there are some confusion with the names. If a structure has the same meaning as on other i.MXes, but a different layout, it should maintain the name (it is not compiled for both). This let to easy understand the meaning, specially if it is valid across architectures. On 11/08/2015 18:19, Adrian Alonso wrote: > * Add system arch level header files > - imx-regs.h: iMX7D SoC system architecture registers > - crm_regs.h: Clock control module registers > - sys_proto.h: helper callback function for SoC setup > > Signed-off-by: Adrian Alonso > Signed-off-by: Peng Fan > Signed-off-by: Ye.Li > --- > Changes for V2: Split patch to easier review process > - Add system arch register definitions > Changes for V3: Resend > Changes for V4: Resend > Changes for V5: Resend > > arch/arm/include/asm/arch-mx7/crm_regs.h | 2813 +++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-mx7/imx-regs.h | 1303 +++++++++++++ > arch/arm/include/asm/arch-mx7/sys_proto.h | 42 + > 3 files changed, 4158 insertions(+) > create mode 100644 arch/arm/include/asm/arch-mx7/crm_regs.h > create mode 100644 arch/arm/include/asm/arch-mx7/imx-regs.h > create mode 100644 arch/arm/include/asm/arch-mx7/sys_proto.h > > diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h > new file mode 100644 > index 0000000..d65d4d9 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h > @@ -0,0 +1,2813 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * Author: > + * Peng Fan > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ > +#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ > + > +#include > +#include > + > +#define CCM_GPR0_OFFSET 0x0 > +#define CCM_OBSERVE0_OFFSET 0x0400 > +#define CCM_SCTRL0_OFFSET 0x0800 > +#define CCM_CCGR0_OFFSET 0x4000 > +#define CCM_ROOT0_TARGET_OFFSET 0x8000 > + > +#ifndef __ASSEMBLY__ > + > +struct mxc_ccm_ccgr { > + uint32_t ccgr; > + uint32_t ccgr_set; > + uint32_t ccgr_clr; > + uint32_t ccgr_tog; > +}; > + > +struct mxc_ccm_root_slice { > + uint32_t target_root; > + uint32_t target_root_set; > + uint32_t target_root_clr; > + uint32_t target_root_tog; > + uint32_t reserved_0[4]; > + uint32_t post; > + uint32_t post_root_set; > + uint32_t post_root_clr; > + uint32_t post_root_tog; > + uint32_t pre; > + uint32_t pre_root_set; > + uint32_t pre_root_clr; > + uint32_t pre_root_tog; > + uint32_t reserved_1[12]; > + uint32_t access_ctrl; > + uint32_t access_ctrl_root_set; > + uint32_t access_ctrl_root_clr; > + uint32_t access_ctrl_root_tog; > +}; > + > +/** CCM - Peripheral register structure */ > +struct mxc_ccm_reg { We have struct ccm_regs - layout is different, but having the same names makes easier if one has to work on multiple SOCs. > + uint32_t gpr0; > + uint32_t gpr0_set; > + uint32_t gpr0_clr; > + uint32_t gpr0_tog; > + uint32_t reserved_0[4092]; > + struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ > + uint32_t reserved_1[3332]; > + struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ > + > +}; > + > +struct mxc_ccm_anatop_reg { and struct anatop_regs > + uint32_t ctrl_24m; /* offset 0x0000 */ > + uint32_t ctrl_24m_set; > + uint32_t ctrl_24m_clr; > + uint32_t ctrl_24m_tog; > + uint32_t rcosc_config0; /* offset 0x0010 */ > + uint32_t rcosc_config0_set; > + uint32_t rcosc_config0_clr; > + uint32_t rcosc_config0_tog; > + uint32_t rcosc_config1; /* offset 0x0020 */ > + uint32_t rcosc_config1_set; > + uint32_t rcosc_config1_clr; > + uint32_t rcosc_config1_tog; > + uint32_t rcosc_config2; /* offset 0x0030 */ > + uint32_t rcosc_config2_set; > + uint32_t rcosc_config2_clr; > + uint32_t rcosc_config2_tog; > + uint8_t reserved_0[16]; > + uint32_t osc_32k; /* offset 0x0050 */ > + uint32_t osc_32k_set; > + uint32_t osc_32k_clr; > + uint32_t osc_32k_tog; > + uint32_t pll_arm; /* offset 0x0060 */ > + uint32_t pll_arm_set; > + uint32_t pll_arm_clr; > + uint32_t pll_arm_tog; > + uint32_t pll_ddr; /* offset 0x0070 */ > + uint32_t pll_ddr_set; > + uint32_t pll_ddr_clr; > + uint32_t pll_ddr_tog; > + uint32_t pll_ddr_ss; /* offset 0x0080 */ > + uint8_t reserved_1[12]; > + uint32_t pll_ddr_num; /* offset 0x0090 */ > + uint8_t reserved_2[12]; > + uint32_t pll_ddr_denom; /* offset 0x00a0 */ > + uint8_t reserved_3[12]; > + uint32_t pll_480; /* offset 0x00b0 */ > + uint32_t pll_480_set; > + uint32_t pll_480_clr; > + uint32_t pll_480_tog; > + uint32_t pfd_480a; /* offset 0x00c0 */ > + uint32_t pfd_480a_set; > + uint32_t pfd_480a_clr; > + uint32_t pfd_480a_tog; > + uint32_t pfd_480b; /* offset 0x00d0 */ > + uint32_t pfd_480b_set; > + uint32_t pfd_480b_clr; > + uint32_t pfd_480b_tog; > + uint32_t pll_enet; /* offset 0x00e0 */ > + uint32_t pll_enet_set; > + uint32_t pll_enet_clr; > + uint32_t pll_enet_tog; > + uint32_t pll_audio; /* offset 0x00f0 */ > + uint32_t pll_audio_set; > + uint32_t pll_audio_clr; > + uint32_t pll_audio_tog; > + uint32_t pll_audio_ss; /* offset 0x0100 */ > + uint8_t reserved_4[12]; > + uint32_t pll_audio_num; /* offset 0x0110 */ > + uint8_t reserved_5[12]; > + uint32_t pll_audio_denom; /* offset 0x0120 */ > + uint8_t reserved_6[12]; > + uint32_t pll_video; /* offset 0x0130 */ > + uint32_t pll_video_set; > + uint32_t pll_video_clr; > + uint32_t pll_video_tog; > + uint32_t pll_video_ss; /* offset 0x0140 */ > + uint8_t reserved_7[12]; > + uint32_t pll_video_num; /* offset 0x0150 */ > + uint8_t reserved_8[12]; > + uint32_t pll_video_denom; /* offset 0x0160 */ > + uint8_t reserved_9[12]; > + uint32_t clk_misc0; /* offset 0x0170 */ > + uint32_t clk_misc0_set; > + uint32_t clk_misc0_clr; > + uint32_t clk_misc0_tog; > + uint32_t clk_rsvd; /* offset 0x0180 */ > + uint8_t reserved_10[124]; > + uint32_t reg_1p0a; /* offset 0x0200 */ > + uint32_t reg_1p0a_set; > + uint32_t reg_1p0a_clr; > + uint32_t reg_1p0a_tog; > + uint32_t reg_1p0d; /* offsest 0x0210 */ > + uint32_t reg_1p0d_set; > + uint32_t reg_1p0d_clr; > + uint32_t reg_1p0d_tog; > + uint32_t reg_hsic_1p2; /* offset 0x0220 */ > + uint32_t reg_hsic_1p2_set; > + uint32_t reg_hsic_1p2_clr; > + uint32_t reg_hsic_1p2_tog; > + uint32_t reg_lpsr_1p0; /* offset 0x0230 */ > + uint32_t reg_lpsr_1p0_set; > + uint32_t reg_lpsr_1p0_clr; > + uint32_t reg_lpsr_1p0_tog; > + uint32_t reg_3p0; /* offset 0x0240 */ > + uint32_t reg_3p0_set; > + uint32_t reg_3p0_clr; > + uint32_t reg_3p0_tog; > + uint32_t reg_snvs; /* offset 0x0250 */ > + uint32_t reg_snvs_set; > + uint32_t reg_snvs_clr; > + uint32_t reg_snvs_tog; > + uint32_t analog_debug_misc0; /* offset 0x0260 */ > + uint32_t analog_debug_misc0_set; > + uint32_t analog_debug_misc0_clr; > + uint32_t analog_debug_misc0_tog; > + uint32_t ref; /* offset 0x0270 */ > + uint32_t ref_set; > + uint32_t ref_clr; > + uint32_t ref_tog; > + uint8_t reserved_11[128]; > + uint32_t tempsense0; /* offset 0x0300 */ > + uint32_t tempsense0_set; > + uint32_t tempsense0_clr; > + uint32_t tempsense0_tog; > + uint32_t tempsense1; /* offset 0x0310 */ > + uint32_t tempsense1_set; > + uint32_t tempsense1_clr; > + uint32_t tempsense1_tog; > + uint32_t tempsense_trim; /* offset 0x0320 */ > + uint32_t tempsense_trim_set; > + uint32_t tempsense_trim_clr; > + uint32_t tempsense_trim_tog; > + uint32_t lowpwr_ctrl; /* offset 0x0330 */ > + uint32_t lowpwr_ctrl_set; > + uint32_t lowpwr_ctrl_clr; > + uint32_t lowpwr_ctrl_tog; > + uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ > + uint32_t snvs_tamper_offset_ctrl_set; > + uint32_t snvs_tamper_offset_ctrl_clr; > + uint32_t snvs_tamper_offset_ctrl_tog; > + uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ > + uint32_t snvs_tamper_pull_ctrl_set; > + uint32_t snvs_tamper_pull_ctrl_clr; > + uint32_t snvs_tamper_pull_ctrl_tog; > + uint32_t snvs_test; /* offset 0x0360 */ > + uint32_t snvs_test_set; > + uint32_t snvs_test_clr; > + uint32_t snvs_test_tog; > + uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ > + uint32_t snvs_tamper_trim_ctrl_set; > + uint32_t snvs_tamper_trim_ctrl_ctrl; > + uint32_t snvs_tamper_trim_ctrl_tog; > + uint32_t snvs_misc_ctrl; /* offset 0x0380 */ > + uint32_t snvs_misc_ctrl_set; > + uint32_t snvs_misc_ctrl_clr; > + uint32_t snvs_misc_ctrl_tog; > + uint8_t reserved_12[112]; > + uint32_t misc; /* offset 0x0400 */ > + uint8_t reserved_13[252]; > + uint32_t adc0; /* offset 0x0500 */ > + uint8_t reserved_14[12]; > + uint32_t adc1; /* offset 0x0510 */ > + uint8_t reserved_15[748]; > + uint32_t digprog; /* offset 0x0800 */ > +}; > +#endif > + > +#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) > + > +#define ANADIG_PLL_LOCK 0x80000000 > + > +#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) > +#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) > +#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) > +#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) > +#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) > + > + > +#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f > +#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B > +#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 > +#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 > + > +/* PLL_ARM Bit Fields */ > +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F > +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 > +#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 > +#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 > +#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 > +#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 > +#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 > +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 > +#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 > +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 > +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 > +#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 > +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 > +#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 > +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 > +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 > +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 > +#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 > +#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 > +#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 > +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 > + > +/* PLL_DDR Bit Fields */ > +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F > +#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 > +#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 > +#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 > +#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 > +#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 > +#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 > +#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 > +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 > +#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 > +#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 > +#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 > +#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 > +#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 > +#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 > +#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 > +#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 > +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 > +#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 > +#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 > +#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 > +#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 > +#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 > + > +/* PLL_480 Bit Fields */ > +#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 > +#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE > +#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 > +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 > +#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 > +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 > +#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 > +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 > +#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 > +#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 > +#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 > +#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 > +#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 > +#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 > +#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 > +#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 > +#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 > +#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 > +#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 > +#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 > +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 > +#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 > +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 > +#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 > +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 > +#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 > +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 > +#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 > +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 > +#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 > +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 > +#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 > +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 > +#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 > +#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 > +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 > +#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 > +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 > +#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 > +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 > +#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 > +#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 > +#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 > +#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 > +#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 > + I am also question if names here should be totally different as we use on i.MX6. Some names are quite similar and I had to guess they have the same meaning (understood, different layout). But if they have the same meaning, why cannot we reuse them ? > +/* PFD_480A Bit Fields */ > +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F > +#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 > +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 > +#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 > +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 > +#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 > +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 > +#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 > +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 > +#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 > +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 > +#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 > +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 > +#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 > +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 > +#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 > +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 > +#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 > +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 > +#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 > +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 > +#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 > +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 > +#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 > +/* PFD_480B Bit Fields */ > +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F > +#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 > +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 > +#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 > +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 > +#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 > +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 > +#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 > +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 > +#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 > +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 > +#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 > +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 > +#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 > +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 > +#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 > +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 > +#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 > +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 > +#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 > +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 > +#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 > +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 > +#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 > + > +/* PLL_ENET Bit Fields */ > +#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 > +#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 > +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 > +#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 > +#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 > +#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 > +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 > +#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 > +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 > +#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 > +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 > +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 > +#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 > +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 > +#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 > +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 > +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 > +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 > +#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 > +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 > +#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 > +#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 > +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 > + > +/* PLL_AUDIO Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 > +/* PLL_AUDIO_SET Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 > +/* PLL_AUDIO_CLR Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 > +/* PLL_AUDIO_TOG Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 > +/* PLL_AUDIO_SS Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu > +#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u > +#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 > +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u > +#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 > +#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))< +/* PLL_AUDIO_NUM Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu > +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u > +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 > +#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* PLL_AUDIO_DENOM Bit Fields */ > +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu > +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 > +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u > +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 > +#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* PLL_VIDEO Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 > +/* PLL_VIDEO_SET Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 > +/* PLL_VIDEO_CLR Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 > +/* PLL_VIDEO_TOG Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu > +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u > +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 > +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u > +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 > +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u > +#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 > +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u > +#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 > +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u > +#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 > +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 > +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 > +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 > +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 > +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 > +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 > +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 > +#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 > +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 > +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 > +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 > +#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u > +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 > +/* PLL_VIDEO_SS Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu > +#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u > +#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 > +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u > +#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 > +#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))< +/* PLL_VIDEO_NUM Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu > +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u > +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 > +#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* PLL_VIDEO_DENOM Bit Fields */ > +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu > +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 > +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u > +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 > +#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* CLK_MISC0 Bit Fields */ > +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu > +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 > +#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u > +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 > +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u > +#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 > +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u > +#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 > +#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u > +#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 > +#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* CLK_MISC0_SET Bit Fields */ > +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu > +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 > +#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u > +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 > +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u > +#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 > +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u > +#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 > +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u > +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 > +#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* CLK_MISC0_CLR Bit Fields */ > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u > +#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 > +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u > +#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 > +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u > +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 > +#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +/* CLK_MISC0_TOG Bit Fields */ > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u > +#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 > +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u > +#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 > +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u > +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 > +#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< + > +/* REG_1P0A Bit Fields */ > +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0A_RSVD0_SHIFT 13 > +#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_BO_MASK 0x10000u > +#define PMU_REG_1P0A_BO_SHIFT 16 > +#define PMU_REG_1P0A_OK_MASK 0x20000u > +#define PMU_REG_1P0A_OK_SHIFT 17 > +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0A_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u > +#define PMU_REG_1P0A_RSVD1_SHIFT 24 > +#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_1P0A_SET Bit Fields */ > +#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 > +#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_SET_BO_MASK 0x10000u > +#define PMU_REG_1P0A_SET_BO_SHIFT 16 > +#define PMU_REG_1P0A_SET_OK_MASK 0x20000u > +#define PMU_REG_1P0A_SET_OK_SHIFT 17 > +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u > +#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 > +#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_1P0A_CLR Bit Fields */ > +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 > +#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u > +#define PMU_REG_1P0A_CLR_BO_SHIFT 16 > +#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u > +#define PMU_REG_1P0A_CLR_OK_SHIFT 17 > +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u > +#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 > +#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_1P0A_TOG Bit Fields */ > +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 > +#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u > +#define PMU_REG_1P0A_TOG_BO_SHIFT 16 > +#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u > +#define PMU_REG_1P0A_TOG_OK_SHIFT 17 > +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u > +#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 > +#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_1P0D Bit Fields */ > +#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0D_RSVD0_SHIFT 13 > +#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_BO_MASK 0x10000u > +#define PMU_REG_1P0D_BO_SHIFT 16 > +#define PMU_REG_1P0D_OK_MASK 0x20000u > +#define PMU_REG_1P0D_OK_SHIFT 17 > +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0D_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u > +#define PMU_REG_1P0D_RSVD1_SHIFT 24 > +#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_1P0D_OVERRIDE_SHIFT 31 > +/* REG_1P0D_SET Bit Fields */ > +#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 > +#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_SET_BO_MASK 0x10000u > +#define PMU_REG_1P0D_SET_BO_SHIFT 16 > +#define PMU_REG_1P0D_SET_OK_MASK 0x20000u > +#define PMU_REG_1P0D_SET_OK_SHIFT 17 > +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u > +#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 > +#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 > +/* REG_1P0D_CLR Bit Fields */ > +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 > +#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u > +#define PMU_REG_1P0D_CLR_BO_SHIFT 16 > +#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u > +#define PMU_REG_1P0D_CLR_OK_SHIFT 17 > +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u > +#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 > +#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 > +/* REG_1P0D_TOG Bit Fields */ > +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u > +#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 > +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u > +#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 > +#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u > +#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 > +#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u > +#define PMU_REG_1P0D_TOG_BO_SHIFT 16 > +#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u > +#define PMU_REG_1P0D_TOG_OK_SHIFT 17 > +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u > +#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 > +#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u > +#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 > +#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 > +/* REG_HSIC_1P2 Bit Fields */ > +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u > +#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 > +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u > +#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 > +#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u > +#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 > +#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u > +#define PMU_REG_HSIC_1P2_BO_SHIFT 16 > +#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u > +#define PMU_REG_HSIC_1P2_OK_SHIFT 17 > +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u > +#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 > +#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u > +#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 > +#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 > +/* REG_HSIC_1P2_SET Bit Fields */ > +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 > +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u > +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 > +#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u > +#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 > +#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u > +#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 > +#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u > +#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 > +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u > +#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 > +#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u > +#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 > +#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 > +/* REG_HSIC_1P2_CLR Bit Fields */ > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u > +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 > +#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u > +#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 > +#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u > +#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 > +#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u > +#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u > +#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 > +#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u > +#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 > +#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 > +/* REG_HSIC_1P2_TOG Bit Fields */ > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u > +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 > +#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u > +#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 > +#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u > +#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 > +#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u > +#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u > +#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 > +#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u > +#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 > +#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u > +#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 > +/* REG_LPSR_1P0 Bit Fields */ > +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u > +#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 > +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u > +#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 > +#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u > +#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 > +#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u > +#define PMU_REG_LPSR_1P0_BO_SHIFT 16 > +#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u > +#define PMU_REG_LPSR_1P0_OK_SHIFT 17 > +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u > +#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 > +#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u > +#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 > +#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_LPSR_1P0_SET Bit Fields */ > +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 > +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u > +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 > +#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u > +#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 > +#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u > +#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 > +#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u > +#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 > +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u > +#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 > +#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u > +#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 > +#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_LPSR_1P0_CLR Bit Fields */ > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u > +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 > +#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u > +#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 > +#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u > +#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 > +#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u > +#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u > +#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 > +#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u > +#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 > +#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_LPSR_1P0_TOG Bit Fields */ > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 > +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u > +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 > +#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 > +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u > +#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 > +#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u > +#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 > +#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u > +#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u > +#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 > +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u > +#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 > +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u > +#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 > +#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u > +#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 > +#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REG_3P0 Bit Fields */ > +#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u > +#define PMU_REG_3P0_ENABLE_BO_SHIFT 1 > +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_3P0_RSVD0_MASK 0x8u > +#define PMU_REG_3P0_RSVD0_SHIFT 3 > +#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u > +#define PMU_REG_3P0_BO_OFFSET_SHIFT 4 > +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u > +#define PMU_REG_3P0_VBUS_SEL_SHIFT 7 > +#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_RSVD1_MASK 0xE000u > +#define PMU_REG_3P0_RSVD1_SHIFT 13 > +#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u > +#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 > +#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u > +#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 > +#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u > +#define PMU_REG_3P0_REG_TEST_SHIFT 18 > +#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u > +#define PMU_REG_3P0_RSVD2_SHIFT 22 > +#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +/* REG_3P0_SET Bit Fields */ > +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u > +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 > +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u > +#define PMU_REG_3P0_SET_RSVD0_SHIFT 3 > +#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u > +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 > +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u > +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 > +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u > +#define PMU_REG_3P0_SET_RSVD1_SHIFT 13 > +#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u > +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 > +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u > +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 > +#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u > +#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 > +#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u > +#define PMU_REG_3P0_SET_RSVD2_SHIFT 22 > +#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +/* REG_3P0_CLR Bit Fields */ > +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u > +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 > +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u > +#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 > +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u > +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 > +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u > +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 > +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u > +#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 > +#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u > +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 > +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u > +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 > +#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u > +#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 > +#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u > +#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 > +#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +/* REG_3P0_TOG Bit Fields */ > +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u > +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 > +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u > +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 > +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u > +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 > +#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u > +#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 > +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u > +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 > +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u > +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 > +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u > +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 > +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u > +#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 > +#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u > +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 > +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u > +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 > +#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u > +#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 > +#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u > +#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 > +#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +/* REF Bit Fields */ > +#define PMU_REF_REFTOP_PWD_MASK 0x1u > +#define PMU_REF_REFTOP_PWD_SHIFT 0 > +#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u > +#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 > +#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u > +#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 > +#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u > +#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 > +#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u > +#define PMU_REF_REFTOP_VBGADJ_SHIFT 4 > +#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_REFTOP_VBGUP_MASK 0x80u > +#define PMU_REF_REFTOP_VBGUP_SHIFT 7 > +#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u > +#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 > +#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_LPBG_SEL_MASK 0x400u > +#define PMU_REF_LPBG_SEL_SHIFT 10 > +#define PMU_REF_LPBG_TEST_MASK 0x800u > +#define PMU_REF_LPBG_TEST_SHIFT 11 > +#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u > +#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 > +#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u > +#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 > +#define PMU_REF_RSVD1_MASK 0xFFFFC000u > +#define PMU_REF_RSVD1_SHIFT 14 > +#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REF_SET Bit Fields */ > +#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u > +#define PMU_REF_SET_REFTOP_PWD_SHIFT 0 > +#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u > +#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 > +#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u > +#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 > +#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u > +#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 > +#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u > +#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 > +#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u > +#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 > +#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u > +#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 > +#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_SET_LPBG_SEL_MASK 0x400u > +#define PMU_REF_SET_LPBG_SEL_SHIFT 10 > +#define PMU_REF_SET_LPBG_TEST_MASK 0x800u > +#define PMU_REF_SET_LPBG_TEST_SHIFT 11 > +#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u > +#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 > +#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u > +#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 > +#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u > +#define PMU_REF_SET_RSVD1_SHIFT 14 > +#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REF_CLR Bit Fields */ > +#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u > +#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 > +#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u > +#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 > +#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u > +#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 > +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u > +#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 > +#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u > +#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 > +#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u > +#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 > +#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u > +#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 > +#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u > +#define PMU_REF_CLR_LPBG_SEL_SHIFT 10 > +#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u > +#define PMU_REF_CLR_LPBG_TEST_SHIFT 11 > +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u > +#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 > +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u > +#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 > +#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u > +#define PMU_REF_CLR_RSVD1_SHIFT 14 > +#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* REF_TOG Bit Fields */ > +#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u > +#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 > +#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u > +#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 > +#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u > +#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 > +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u > +#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 > +#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u > +#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 > +#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u > +#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 > +#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u > +#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 > +#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u > +#define PMU_REF_TOG_LPBG_SEL_SHIFT 10 > +#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u > +#define PMU_REF_TOG_LPBG_TEST_SHIFT 11 > +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u > +#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 > +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u > +#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 > +#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u > +#define PMU_REF_TOG_RSVD1_SHIFT 14 > +#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* LOWPWR_CTRL Bit Fields */ > +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u > +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 > +#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu > +#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 > +#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u > +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 > +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u > +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 > +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u > +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 > +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u > +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 > +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u > +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 > +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u > +#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 > +#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u > +#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 > +#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u > +#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 > +#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))< +/* LOWPWR_CTRL_SET Bit Fields */ > +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u > +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 > +#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu > +#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 > +#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u > +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 > +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u > +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 > +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u > +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 > +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u > +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 > +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u > +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 > +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u > +#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 > +#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u > +#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 > +#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u > +#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 > +#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))< +/* LOWPWR_CTRL_CLR Bit Fields */ > +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u > +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 > +#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu > +#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 > +#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u > +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 > +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u > +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 > +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u > +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 > +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u > +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 > +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u > +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 > +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u > +#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 > +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u > +#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 > +#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u > +#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 > +#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))< +/* LOWPWR_CTRL_TOG Bit Fields */ > +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u > +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 > +#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu > +#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 > +#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u > +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 > +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u > +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 > +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u > +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 > +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u > +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 > +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u > +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 > +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u > +#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 > +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u > +#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 > +#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))< +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u > +#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 > +#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))< + > + > +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 > +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE1 Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 > +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< +/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))< +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 > +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< + > + > +#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) This is an usage forbidden in u-boot (I know it is ok in Linux). Registers are accessed by structures and not with offsets. You can rewrite the macro using structures to cgr instead of offsets. > +#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) > +#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) > +#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) > +#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) > + > +#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) > +#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) > +#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) > +#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) > +#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) > + > +#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8) > +#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) > +#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) > +#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) > +#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) > + > +#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12) > +#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) > +#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) > +#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) > +#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) > + > +#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) > +#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) > +#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i)) > +#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i)) > +#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i)) > + > +#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i)) > +#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i)) > +#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i)) > +#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i)) > +#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i)) > + > +#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i)) > +#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) > +#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i)) > +#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i)) > +#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i)) > + > +#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i)) > +#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) > +#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i)) > +#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i)) > +#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) > + > +#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i)) > +#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) > +#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i)) > +#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i)) > +#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) > + > +#define CCM_CLK_ON_MSK 0x03 > + > +#define CCM_ROOT_TGT_POST_DIV_SHIFT 0 > +#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 > +#define CCM_ROOT_TGT_MUX_SHIFT 24 > +#define CCM_ROOT_TGT_ENABLE_SHIFT 28 > +#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F > +#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) > +#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) > +#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) > + > +#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) > +#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) > +#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) > + > +/* > + * Field values definition for clock slice TARGET register > + */ > + > +#define CLK_ROOT_ON 0x10000000 > +#define CLK_ROOT_OFF 0x0 > +#define CLK_ROOT_ENABLE_MASK 0x10000000 > +#define CLK_ROOT_ENABLE_SHIFT 28 > + > +#define CLK_ROOT_ALT0 0x00000000 > +#define CLK_ROOT_ALT1 0x01000000 > +#define CLK_ROOT_ALT2 0x02000000 > +#define CLK_ROOT_ALT3 0x03000000 > +#define CLK_ROOT_ALT4 0x04000000 > +#define CLK_ROOT_ALT5 0x05000000 > +#define CLK_ROOT_ALT6 0x06000000 > +#define CLK_ROOT_ALT7 0x07000000 > + > + > +#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 > +#define CLK_ROOT_POST_DIV_MASK 0x0000003f > +#define CLK_ROOT_POST_DIV_SHIFT 0 > +#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) > + > +#define CLK_ROOT_AUTO_DIV_MASK 0x00000700 > +#define CLK_ROOT_AUTO_DIV_SHIFT 8 > +#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) > + > +#define CLK_ROOT_AUTO_EN_MASK 0x00001000 > +#define CLK_ROOT_AUTO_EN 0x00001000 > + > +#define CLK_ROOT_PRE_DIV_MASK 0x00070000 > +#define CLK_ROOT_PRE_DIV_SHIFT 16 > +#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) > + > +#define CLK_ROOT_MUX_MASK 0x07000000 > +#define CLK_ROOT_MUX_SHIFT 24 > + > +#define CLK_ROOT_EN_MASK 0x10000000 > + > +#define CLK_ROOT_AUTO_ON 0x00001000 > +#define CLK_ROOT_AUTO_OFF 0x0 > + > +/* ARM_A7_CLK_ROOT */ > +#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* ARM_M4_CLK_ROOT */ > +#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* ARM_M0_CLK_ROOT */ > +#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* MAIN_AXI_CLK_ROOT */ > +#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > + > +/* DISP_AXI_CLK_ROOT */ > +#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > + > +/* ENET_AXI_CLK_ROOT */ > +#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > + > +/* NAND_USDHC_BUS_CLK_ROOT */ > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 > + > +/* AHB_CLK_ROOT */ > +#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 > +#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 > +#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 > + > +/* DRAM_PHYM_CLK_ROOT */ > +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 > +#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 > + > +/* DRAM_CLK_ROOT */ > +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 > +#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 > + > +/* DRAM_PHYM_ALT_CLK_ROOT */ > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 > + > +/* DRAM_ALT_CLK_ROOT */ > +#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 > +#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > + > +/* USB_HSIC_CLK_ROOT */ > +#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 > + > +/* PCIE_CTRL_CLK_ROOT */ > +#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 > +#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 > + > +/* PCIE_PHY_CLK_ROOT */ > +#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 > +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 > +#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 > +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 > +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 > +#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* EPDC_PIXEL_CLK_ROOT */ > +#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 > +#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > + > +/* LCDIF_PIXEL_CLK_ROOT */ > +#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 > + > +/* MIPI_DSI_EXTSER_CLK_ROOT */ > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 > +#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > + > +/* MIPI_CSI_WARP_CLK_ROOT */ > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 > +#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > + > +/* MIPI_DPHY_REF_CLK_ROOT */ > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* SAI1_CLK_ROOT */ > +#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 > + > +/* SAI2_CLK_ROOT */ > +#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 > + > +/* SAI3_CLK_ROOT */ > +#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* SPDIF_CLK_ROOT */ > +#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* ENET1_REF_CLK_ROOT */ > +#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 > + > +/* ENET1_TIME_CLK_ROOT */ > +#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 > +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 > +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 > +#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* ENET2_REF_CLK_ROOT */ > +#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 > + > +/* ENET2_TIME_CLK_ROOT */ > +#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 > +#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 > +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 > +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 > +#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* ENET_PHY_REF_CLK_ROOT */ > +#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > + > +/* EIM_CLK_ROOT */ > +#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 > +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 > +#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* NAND_CLK_ROOT */ > +#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 > +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 > +#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 > +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 > +#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > + > +/* QSPI_CLK_ROOT */ > +#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 > +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 > +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 > +#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > + > +/* USDHC1_CLK_ROOT */ > +#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > + > +/* USDHC2_CLK_ROOT */ > +#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > + > +/* USDHC3_CLK_ROOT */ > +#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 > + > +/* CAN1_CLK_ROOT */ > +#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 > +#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 > +#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 > +#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 > +#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 > + > +/* CAN2_CLK_ROOT */ > +#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 > +#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 > +#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 > +#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 > +#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* I2C1_CLK_ROOT */ > +#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 > +#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 > +#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 > + > +/* I2C2_CLK_ROOT */ > +#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 > +#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 > +#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 > + > +/* I2C3_CLK_ROOT */ > +#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 > +#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 > +#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 > + > +/* I2C4_CLK_ROOT */ > +#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 > +#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 > +#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 > +#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 > +#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 > + > +/* UART1_CLK_ROOT */ > +#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* UART2_CLK_ROOT */ > +#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 > + > +/* UART3_CLK_ROOT */ > +#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* UART4_CLK_ROOT */ > +#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 > + > +/* UART5_CLK_ROOT */ > +#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* UART6_CLK_ROOT */ > +#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 > + > +/* UART7_CLK_ROOT */ > +#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 > +#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > +#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > +#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 > + > +/* ECSPI1_CLK_ROOT */ > +#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* ECSPI2_CLK_ROOT */ > +#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* ECSPI3_CLK_ROOT */ > +#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* ECSPI4_CLK_ROOT */ > +#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 > +#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* PWM1_CLK_ROOT */ > +#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 > + > +/* PWM2_CLK_ROOT */ > +#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 > + > +/* PWM3_CLK_ROOT */ > +#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > + > +/* PWM4_CLK_ROOT */ > +#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 > + > +/* FLEXTIMER1_CLK_ROOT */ > +#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 > + > +/* FLEXTIMER2_CLK_ROOT */ > +#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > +#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 > + > +/* SIM1_CLK_ROOT */ > +#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 > + > +/* SIM2_CLK_ROOT */ > +#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 > +#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 > +#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 > + > +/* GPT1_CLK_ROOT */ > +#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 > +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 > +#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 > + > +/* GPT2_CLK_ROOT */ > +#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 > +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 > +#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 > + > +/* GPT3_CLK_ROOT */ > +#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 > +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 > +#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* GPT4_CLK_ROOT */ > +#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 > +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 > +#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 > +#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 > +#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 > +#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 > +#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 > + > +/* TRACE_CLK_ROOT */ > +#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 > +#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 > +#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 > +#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 > + > +/* WDOG_CLK_ROOT */ > +#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 > +#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 > +#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 > +#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 > + > +/* CSI_MCLK_CLK_ROOT */ > +#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* AUDIO_MCLK_CLK_ROOT */ > +#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 > + > +/* WRCLK_CLK_ROOT */ > +#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 > +#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 > + > +/* IPP_DO_CLKO1 */ > +#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 > +#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 > +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 > +#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 > +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 > +#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 > +#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 > +#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 > + > +/* IPP_DO_CLKO2 */ > +#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 > +#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 > +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 > +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 > +#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 > +#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 > +#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 > +#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 > + > +#endif > diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h > new file mode 100644 > index 0000000..8d6bbd5 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h > @@ -0,0 +1,1303 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ASM_ARCH_MX7_IMX_REGS_H__ > +#define __ASM_ARCH_MX7_IMX_REGS_H__ > + > +#define ARCH_MXC > + > +#define CONFIG_SYS_CACHELINE_SIZE 64 > + > +#define ROM_SW_INFO_ADDR 0x000001E8 > +#define ROMCP_ARB_BASE_ADDR 0x00000000 > +#define ROMCP_ARB_END_ADDR 0x00017FFF > +#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR > +#define CAAM_ARB_BASE_ADDR 0x00100000 > +#define CAAM_ARB_END_ADDR 0x00107FFF > +#define GIC400_ARB_BASE_ADDR 0x31000000 > +#define GIC400_ARB_END_ADDR 0x31007FFF > +#define APBH_DMA_ARB_BASE_ADDR 0x33000000 > +#define APBH_DMA_ARB_END_ADDR 0x33007FFF > +#define M4_BOOTROM_BASE_ADDR 0x00180000 > + > +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR > +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) > +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) > + > +/* GPV - PL301 configuration ports */ > +#define GPV0_BASE_ADDR 0x32000000 > +#define GPV1_BASE_ADDR 0x32100000 > +#define GPV2_BASE_ADDR 0x32200000 > +#define GPV3_BASE_ADDR 0x32300000 > +#define GPV4_BASE_ADDR 0x32400000 > +#define GPV5_BASE_ADDR 0x32500000 > +#define GPV6_BASE_ADDR 0x32600000 > +#define GPV7_BASE_ADDR 0x32700000 > + > +#define OCRAM_ARB_BASE_ADDR 0x00900000 > +#define OCRAM_ARB_END_ADDR 0x0091FFFF > +#define OCRAM_EPDC_BASE_ADDR 0x00920000 > +#define OCRAM_EPDC_END_ADDR 0x0093FFFF > +#define OCRAM_PXP_BASE_ADDR 0x00940000 > +#define OCRAM_PXP_END_ADDR 0x00947FFF > +#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR > +#define IRAM_SIZE 0x00020000 > + > +#define AIPS1_ARB_BASE_ADDR 0x30000000 > +#define AIPS1_ARB_END_ADDR 0x303FFFFF > +#define AIPS2_ARB_BASE_ADDR 0x30400000 > +#define AIPS2_ARB_END_ADDR 0x307FFFFF > +#define AIPS3_ARB_BASE_ADDR 0x30800000 > +#define AIPS3_ARB_END_ADDR 0x30BFFFFF > + > +#define WEIM_ARB_BASE_ADDR 0x28000000 > +#define WEIM_ARB_END_ADDR 0x2FFFFFFF > + > +#define QSPI0_ARB_BASE_ADDR 0x60000000 > +#define QSPI0_ARB_END_ADDR 0x6FFFFFFF > +#define PCIE_ARB_BASE_ADDR 0x40000000 > +#define PCIE_ARB_END_ADDR 0x4FFFFFFF > +#define PCIE_REG_BASE_ADDR 0x33800000 > +#define PCIE_REG_END_ADDR 0x33803FFF > + > +#define MMDC0_ARB_BASE_ADDR 0x80000000 > +#define MMDC0_ARB_END_ADDR 0xBFFFFFFF > +#define MMDC1_ARB_BASE_ADDR 0xC0000000 > +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF > + > +/* Cortex-A9 MPCore private memory region */ > +#define ARM_PERIPHBASE 0x31000000 > +#define SCU_BASE_ADDR ARM_PERIPHBASE > +#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) > +#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) > + > + > +/* Defines for Blocks connected via AIPS (SkyBlue) */ > +#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR > +#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR > +#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR > + > +/* DAP base-address */ > +#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR > + > +/* AIPS_TZ#1- On Platform */ > +#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) > +/* AIPS_TZ#1- Off Platform */ > +#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) > + > +#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR > +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) > +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) > +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) > +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) > +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) > +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) > +#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) > +#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) > +#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) > +#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) > +#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) > +#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) > +#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) > +#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR > +#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) > +#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) > +#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) > +#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) > +#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) > +#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) > +#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR > +#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) > +#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) > +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) > +#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) > +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) > +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) > +#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) > +#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) > +#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) > +#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) > +#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) > + > +/* AIPS_TZ#2- On Platform */ > +#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) > +/* AIPS_TZ#2- Off Platform */ > +#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) > +#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) > +#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) > +#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) > +#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) > +#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) > +#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) > +#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) > +#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) > +#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) > +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) > +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) > +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) > +#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) > +#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) > +#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR > +#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) > +#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) > +#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) > +#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) > +#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) > +#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) > +#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) > +#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) > +#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) > +#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) > +#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) > +#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) > + > +/* AIPS_TZ#3 - Global enable (0) */ > +#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) > +#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) > +#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) > +#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) > +#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) > +#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) > +#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) > +#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) > +#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) > +#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) > +#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) > + > +/* AIPS_TZ#3- On Platform */ > +#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) > +/* AIPS_TZ#3- Off Platform */ > +#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) > +#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR > +#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) > +#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) > +#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) > +#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) > +#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) > +#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) > +#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) > +#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) > +#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) > +#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) > +#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) > +#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) > +#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) > +#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) > +#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) > +#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) > +#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) > +#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) > +#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) > +#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) > +#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) > +#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) > +#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) > +#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) > +#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) > +#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) > +#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) > +#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) > + > +#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR > +#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR > + > +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR > +#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR > + > +#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR > + > +#define FEC_QUIRK_ENET_MAC > +#define SNVS_LPGPR 0x68 > + > +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) > +#include > + > +extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); > + > +/* System Reset Controller (SRC) */ > +struct src { > + u32 scr; > + u32 a7rcr0; > + u32 a7rcr1; > + u32 m4rcr; > + u32 reserved1; > + u32 ercr; > + u32 reserved2; > + u32 hsicphy_rcr; > + u32 usbophy1_rcr; > + u32 usbophy2_rcr; > + u32 mipiphy_rcr; > + u32 pciephy_rcr; > + u32 reserved3[10]; > + u32 sbmr1; > + u32 srsr; > + u32 reserved4[2]; > + u32 sisr; > + u32 simr; > + u32 sbmr2; > + u32 gpr1; > + u32 gpr2; > + u32 gpr3; > + u32 gpr4; > + u32 gpr5; > + u32 gpr6; > + u32 gpr7; > + u32 gpr8; > + u32 gpr9; > + u32 gpr10; > + u32 reserved5[985]; > + u32 ddrc_rcr; > +}; > + > +/* GPR0 Bit Fields */ > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u > +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 > +/* GPR1 Bit Fields */ > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 On i.MX6, the logic for defining bits is #define _NAME_OFFSET # define _NAME_MASK (x << OFSSET) you are doing her ethe same in a different way. Can wwe use the same approach ? > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 > +#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u > +#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 > +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u > +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 > +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u > +#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 > +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u > +#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 > +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u > +#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 > +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u > +#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 > +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u > +#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 > +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u > +#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 > +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u > +#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 > +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u > +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 > +#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u > +#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 > +/* GPR2 Bit Fields */ > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u > +#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u > +#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u > +#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u > +#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 > +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u > +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 > +#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u > +#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 > +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u > +#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 > +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u > +#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 > +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u > +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 > +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u > +#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u > +#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 > +/* GPR3 Bit Fields */ > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u > +#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u > +#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 > +/* GPR4 Bit Fields */ > +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u > +#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 > +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u > +#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 > +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u > +#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 > +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u > +#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 > +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u > +#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 > +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u > +#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 > +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u > +#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 > +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u > +#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 > +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u > +#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 > +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u > +#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 > +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u > +#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 > +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u > +#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 > +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u > +#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 > +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u > +#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 > +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u > +#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 > +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u > +#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 > +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u > +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 > +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u > +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 > +#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))< +/* GPR5 Bit Fields */ > +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u > +#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 > +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u > +#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 > +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u > +#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 > +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u > +#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 > +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u > +#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 > +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u > +#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 > +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u > +#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 > +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u > +#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 > +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u > +#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 > +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u > +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 > +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u > +#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 > +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u > +#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 > +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u > +#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u > +#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 > +/* GPR6 Bit Fields */ > +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u > +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 > +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u > +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 > +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u > +#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 > +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u > +#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 > +/* GPR7 Bit Fields */ > +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u > +#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 > +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u > +#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 > +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u > +#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 > +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u > +#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 > +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u > +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 > +#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u > +#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 > +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u > +#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 > +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u > +#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 > +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u > +#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 > +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u > +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 > +#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u > +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 > +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u > +#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 > +/* GPR8 Bit Fields */ > +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u > +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 > +#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u > +#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 > +/* GPR9 Bit Fields */ > +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u > +#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 > +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu > +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 > +#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))< +/* GPR10 Bit Fields */ > +#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u > +#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 > +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u > +#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 > +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u > +#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 > +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u > +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 > +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u > +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 > +#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))< +/* GPR11 Bit Fields */ > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 > +#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))< +/* GPR12 Bit Fields */ > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 > +#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))< +/* GPR13 Bit Fields */ > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u > +#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u > +#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u > +#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 > +/* GPR14 Bit Fields */ > +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u > +#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 > +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u > +#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 > +/* GPR15 Bit Fields */ > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 > +#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))< +/* GPR16 Bit Fields */ > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 > +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u > +#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 > +/* GPR17 Bit Fields */ > +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu > +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 > +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u > +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 > +#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))< +/* GPR18 Bit Fields */ > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 > +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u > +#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 > +/* GPR19 Bit Fields */ > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u > +#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 > +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u > +#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 > +/* GPR20 Bit Fields */ > +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu > +#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u > +#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u > +#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u > +#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u > +#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u > +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 > +#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))< +/* GPR21 Bit Fields */ > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 > +#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u > +#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 > +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u > +#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 > +/* GPR22 Bit Fields */ > +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u > +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 > +#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))< +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u > +#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 > +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u > +#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 > +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u > +#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 > +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u > +#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 > +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u > +#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 > +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u > +#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 > +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u > +#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 > + > +#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) > +#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) > +#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) > + > +struct iomuxc { > + u32 gpr[23]; > + /* mux and pad registers */ > +}; > + > +struct iomuxc_gpr_base_regs { > + u32 gpr[23]; /* 0x000 */ > +}; > + > +/* ECSPI registers */ > +struct cspi_regs { > + u32 rxdata; > + u32 txdata; > + u32 ctrl; > + u32 cfg; > + u32 intr; > + u32 dma; > + u32 stat; > + u32 period; > +}; > + > +/* > + * CSPI register definitions > + */ > +#define MXC_ECSPI > +#define MXC_CSPICTRL_EN (1 << 0) > +#define MXC_CSPICTRL_MODE (1 << 1) > +#define MXC_CSPICTRL_XCH (1 << 2) > +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) > +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) > +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) > +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) > +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) > +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) > +#define MXC_CSPICTRL_MAXBITS 0xfff > +#define MXC_CSPICTRL_TC (1 << 7) > +#define MXC_CSPICTRL_RXOVF (1 << 6) > +#define MXC_CSPIPERIOD_32KHZ (1 << 15) > +#define MAX_SPI_BYTES 32 > + > +/* Bit position inside CTRL register to be associated with SS */ > +#define MXC_CSPICTRL_CHAN 18 > + > +/* Bit position inside CON register to be associated with SS */ > +#define MXC_CSPICON_PHA 0 /* SCLK phase control */ > +#define MXC_CSPICON_POL 4 /* SCLK polarity */ > +#define MXC_CSPICON_SSPOL 12 /* SS polarity */ > +#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ > + > +#define MXC_SPI_BASE_ADDRESSES \ > + ECSPI1_BASE_ADDR, \ > + ECSPI2_BASE_ADDR, \ > + ECSPI3_BASE_ADDR, \ > + ECSPI4_BASE_ADDR > + > +struct ocotp_regs { > + u32 ctrl; > + u32 ctrl_set; > + u32 ctrl_clr; > + u32 ctrl_tog; > + u32 timing; > + u32 rsvd0[3]; > + u32 data0; > + u32 rsvd1[3]; > + u32 data1; > + u32 rsvd2[3]; > + u32 data2; > + u32 rsvd3[3]; > + u32 data3; > + u32 rsvd4[3]; > + u32 read_ctrl; > + u32 rsvd5[3]; > + u32 read_fuse_data0; > + u32 rsvd6[3]; > + u32 read_fuse_data1; > + u32 rsvd7[3]; > + u32 read_fuse_data2; > + u32 rsvd8[3]; > + u32 read_fuse_data3; > + u32 rsvd9[3]; > + u32 sw_sticky; > + u32 rsvd10[3]; > + u32 scs; > + u32 scs_set; > + u32 scs_clr; > + u32 scs_tog; > + u32 crc_addr; > + u32 rsvd11[3]; > + u32 crc_value; > + u32 rsvd12[3]; > + u32 version; > + u32 rsvd13[0xc3]; > + > + struct fuse_bank { /* offset 0x400 */ > + u32 fuse_regs[0x10]; > + } bank[16]; > +}; > + > +struct fuse_bank0_regs { > + u32 lock; > + u32 rsvd0[3]; > + u32 tester0; > + u32 rsvd1[3]; > + u32 tester1; > + u32 rsvd2[3]; > + u32 tester2; > + u32 rsvd3[3]; > +}; > + > +struct fuse_bank1_regs { > + u32 tester3; > + u32 rsvd0[3]; > + u32 tester4; > + u32 rsvd1[3]; > + u32 tester5; > + u32 rsvd2[3]; > + u32 cfg0; > + u32 rsvd3[3]; > +}; > + > +struct fuse_bank2_regs { > + u32 cfg1; > + u32 rsvd0[3]; > + u32 cfg2; > + u32 rsvd1[3]; > + u32 cfg3; > + u32 rsvd2[3]; > + u32 cfg4; > + u32 rsvd3[3]; > +}; > + > +struct fuse_bank3_regs { > + u32 mem_trim0; > + u32 rsvd0[3]; > + u32 mem_trim1; > + u32 rsvd1[3]; > + u32 ana0; > + u32 rsvd2[3]; > + u32 ana1; > + u32 rsvd3[3]; > +}; > + > +struct fuse_bank8_regs { > + u32 sjc_resp_low; > + u32 rsvd0[3]; > + u32 sjc_resp_high; > + u32 rsvd1[3]; > + u32 usb_id; > + u32 rsvd2[3]; > + u32 field_return; > + u32 rsvd3[3]; > +}; > + > +struct fuse_bank9_regs { > + u32 mac_addr0; > + u32 rsvd0[3]; > + u32 mac_addr1; > + u32 rsvd1[3]; > + u32 mac_addr2; > + u32 rsvd2[7]; > +}; > + > +struct aipstz_regs { > + u32 mprot0; > + u32 mprot1; > + u32 rsvd[0xe]; > + u32 opacr0; > + u32 opacr1; > + u32 opacr2; > + u32 opacr3; > + u32 opacr4; > +}; > + > +struct wdog_regs { > + u16 wcr; /* Control */ > + u16 wsr; /* Service */ > + u16 wrsr; /* Reset Status */ > + u16 wicr; /* Interrupt Control */ > + u16 wmcr; /* Miscellaneous Control */ > +}; > + > +struct dbg_monitor_regs { > + u32 ctrl[4]; /* Control */ > + u32 master_en[4]; /* Master enable */ > + u32 irq[4]; /* IRQ */ > + u32 trap_addr_low[4]; /* Trap address low */ > + u32 trap_addr_high[4]; /* Trap address high */ > + u32 trap_id[4]; /* Trap ID */ > + u32 snvs_addr[4]; /* SNVS address */ > + u32 snvs_data[4]; /* SNVS data */ > + u32 snvs_info[4]; /* SNVS info */ > + u32 version[4]; /* Version */ > +}; > + > +struct rdc_regs { > + u32 vir; /* Version information */ > + u32 reserved1[8]; > + u32 stat; /* Status */ > + u32 intctrl; /* Interrupt and Control */ > + u32 intstat; /* Interrupt Status */ > + u32 reserved2[116]; > + u32 mda[27]; /* Master Domain Assignment */ > + u32 reserved3[101]; > + u32 pdap[118]; /* Peripheral Domain Access Permissions */ > + u32 reserved4[138]; > + struct { > + u32 mrsa; /* Memory Region Start Address */ > + u32 mrea; /* Memory Region End Address */ > + u32 mrc; /* Memory Region Control */ > + u32 mrvs; /* Memory Region Violation Status */ > + } mem_region[52]; > +}; > + > +struct rdc_sema_regs { > + u8 gate[64]; /* Gate */ > + u16 rstgt; /* Reset Gate */ > +}; > + > +/* eLCDIF controller registers */ > +struct mxs_lcdif_regs { What about arch/arm/include/asm/arch-mxs/regs-lcdif.h ? The layourt is identical up to... > + u32 hw_lcdif_ctrl; /* 0x00 */ > + u32 hw_lcdif_ctrl_set; > + u32 hw_lcdif_ctrl_clr; > + u32 hw_lcdif_ctrl_tog; > + u32 hw_lcdif_ctrl1; /* 0x10 */ > + u32 hw_lcdif_ctrl1_set; > + u32 hw_lcdif_ctrl1_clr; > + u32 hw_lcdif_ctrl1_tog; > + u32 hw_lcdif_ctrl2; /* 0x20 */ > + u32 hw_lcdif_ctrl2_set; > + u32 hw_lcdif_ctrl2_clr; > + u32 hw_lcdif_ctrl2_tog; > + u32 hw_lcdif_transfer_count; /* 0x30 */ > + u32 reserved1[3]; > + u32 hw_lcdif_cur_buf; /* 0x40 */ > + u32 reserved2[3]; > + u32 hw_lcdif_next_buf; /* 0x50 */ > + u32 reserved3[3]; > + u32 hw_lcdif_timing; /* 0x60 */ > + u32 reserved4[3]; > + u32 hw_lcdif_vdctrl0; /* 0x70 */ > + u32 hw_lcdif_vdctrl0_set; > + u32 hw_lcdif_vdctrl0_clr; > + u32 hw_lcdif_vdctrl0_tog; > + u32 hw_lcdif_vdctrl1; /* 0x80 */ > + u32 reserved5[3]; > + u32 hw_lcdif_vdctrl2; /* 0x90 */ > + u32 reserved6[3]; > + u32 hw_lcdif_vdctrl3; /* 0xa0 */ > + u32 reserved7[3]; > + u32 hw_lcdif_vdctrl4; /* 0xb0 */ > + u32 reserved8[3]; > + u32 hw_lcdif_dvictrl0; /* 0xc0 */ > + u32 reserved9[3]; > + u32 hw_lcdif_dvictrl1; /* 0xd0 */ > + u32 reserved10[3]; > + u32 hw_lcdif_dvictrl2; /* 0xe0 */ > + u32 reserved11[3]; > + u32 hw_lcdif_dvictrl3; /* 0xf0 */ > + u32 reserved12[3]; > + u32 hw_lcdif_dvictrl4; /* 0x100 */ > + u32 reserved13[3]; > + u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */ > + u32 reserved14[3]; > + u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */ > + u32 reserved15[3]; > + u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */ > + u32 reserved16[3]; > + u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */ > + u32 reserved17[3]; > + u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */ > + u32 reserved18[3]; > + u32 hw_lcdif_csc_offset; /* 0x160 */ > + u32 reserved19[3]; > + u32 hw_lcdif_csc_limit; /* 0x170 */ > + u32 reserved20[3]; > + u32 hw_lcdif_data; /* 0x180 */ > + u32 reserved21[3]; > + u32 hw_lcdif_bm_error_stat; /* 0x190 */ > + u32 reserved22[3]; > + u32 hw_lcdif_crc_stat; /* 0x1a0 */ > + u32 reserved23[3]; > + u32 hw_lcdif_lcdif_stat; /* 0x1b0 */ > + u32 reserved24[3]; > + u32 hw_lcdif_version; /* 0x1c0 */ > + u32 reserved25[3]; > + u32 hw_lcdif_debug0; /* 0x1d0 */ > + u32 reserved26[3]; > + u32 hw_lcdif_debug1; /* 0x1e0 */ > + u32 reserved27[3]; > + u32 hw_lcdif_debug2; /* 0x1f0 */ ...here ! > + u32 reserved28[3]; > + u32 hw_lcdif_thres; /* 0x200 */ > + u32 reserved29[3]; > + u32 hw_lcdif_as_ctrl; /* 0x210 */ > + u32 reserved30[3]; > + u32 hw_lcdif_as_buf; /* 0x220 */ > + u32 reserved31[3]; > + u32 hw_lcdif_as_next_buf; /* 0x230 */ > + u32 reserved32[3]; > + u32 hw_lcdif_as_clrkeylow; /* 0x240 */ > + u32 reserved33[3]; > + u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */ > + u32 reserved34[3]; > + u32 hw_lcdif_as_sync_delay; /* 0x260 */ > + u32 reserved35[3]; > + u32 hw_lcdif_as_debug3; /* 0x270 */ > + u32 reserved36[3]; > + u32 hw_lcdif_as_debug4; /* 0x280 */ > + u32 reserved37[3]; > + u32 hw_lcdif_as_debug5; /* 0x290 */ > +}; > + > +#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR > + > +#define LCDIF_CTRL_SFTRST (1 << 31) > +#define LCDIF_CTRL_CLKGATE (1 << 30) > +#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) > +#define LCDIF_CTRL_READ_WRITEB (1 << 28) > +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) > +#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) > +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) > +#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 > +#define LCDIF_CTRL_DVI_MODE (1 << 20) > +#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) > +#define LCDIF_CTRL_VSYNC_MODE (1 << 18) > +#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) > +#define LCDIF_CTRL_DATA_SELECT (1 << 16) > +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) > +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 > +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) > +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) > +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) > +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) > +#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 > +#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) > +#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) > +#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) > +#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) > +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) > +#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) > +#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) > +#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) > +#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) > +#define LCDIF_CTRL_RUN (1 << 0) > + > +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) > +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) > +#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) > +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) > +#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) > +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) > +#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) > +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) > +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) > +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 > +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) > +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) > +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) > +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) > +#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) > +#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) > +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) > +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) > +#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) > +#define LCDIF_CTRL1_MODE86 (1 << 1) > +#define LCDIF_CTRL1_RESET (1 << 0) > + > +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) > +#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 > +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) > +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) > +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) > +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) > +#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) > +#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) > +#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) > +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) > +#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) > +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) > +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) > +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) > +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 > +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) > +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 > + > +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) > +#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 > +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) > +#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 > + > +#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff > +#define LCDIF_CUR_BUF_ADDR_OFFSET 0 > + > +#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff > +#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 > + > +#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) > +#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 > +#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) > +#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 > +#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) > +#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 > +#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) > +#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 > + > +#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) > +#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) > +#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) > +#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) > +#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) > +#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) > +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) > +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) > +#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) > +#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) > +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff > +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 > + > +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff > +#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 > + > +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) > +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 > +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff > +#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 > + > +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) > +#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) > +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) > +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 > +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) > +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 > + > +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) > +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 > +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) > +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff > +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 > + See my comments related to regs-lcdif.h > + > +extern void check_cpu_temperature(void); > + > +extern void pcie_power_up(void); > +extern void pcie_power_off(void); > + > +/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB > + * If boot from the other mode, USB0_PWD will keep reset value > + */ > +#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ > + readl(USBOTG2_IPS_BASE_ADDR + 0x158)) > +#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) > + > +/* Boot device type */ > +#define BOOT_TYPE_SD 0x1 > +#define BOOT_TYPE_MMC 0x2 > +#define BOOT_TYPE_NAND 0x3 > +#define BOOT_TYPE_QSPI 0x4 > +#define BOOT_TYPE_WEIM 0x5 > +#define BOOT_TYPE_SPINOR 0x6 > + > +struct bootrom_sw_info { > + u8 reserved_1; > + u8 boot_dev_instance; > + u8 boot_dev_type; > + u8 reserved_2; > + u32 arm_core_freq; > + u32 axi_freq; > + u32 ddr_freq; > + u32 gpt1_freq; > + u32 reserved_3[3]; > +}; > + > +#endif /* __ASSEMBLER__*/ > +#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h > new file mode 100644 > index 0000000..b5533d0 > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7/sys_proto.h > @@ -0,0 +1,42 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef _SYS_PROTO_H_ > +#define _SYS_PROTO_H_ > + > +#include > +#include "../arch-imx/cpu.h" > + > +#define is_soc_rev(rev) ((int)((get_cpu_rev() & 0xFF) - rev)) > +u32 get_cpu_rev(void); > + Peng has cleaned upand factorize these functions. I have now applied his patches, please use the same mechanism for i.MX7, too - thanks ! > +/* returns MXC_CPU_ value */ > +#define cpu_type(rev) (((rev) >> 12)&0xff) > + > +/* use with MXC_CPU_ constants */ > +#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu) > + > +const char *get_imx_type(u32 imxtype); > +unsigned imx_ddr_size(void); > +void set_wdog_reset(struct wdog_regs *wdog); > + > +/* > + * Initializes on-chip ethernet controllers. > + * to override, implement board_eth_init() > + */ > + > +int fecmxc_initialize(bd_t *bis); > +u32 get_ahb_clk(void); > +u32 get_periph_clk(void); > + > +int mxs_reset_block(struct mxs_register_32 *reg); > +int mxs_wait_mask_set(struct mxs_register_32 *reg, > + uint32_t mask, > + unsigned int timeout); > +int mxs_wait_mask_clr(struct mxs_register_32 *reg, > + uint32_t mask, > + unsigned int timeout); > +#endif > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================