[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Marcel Ziswiler]

Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.

While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.

This fixes an issue of the Colibri T20 being stuck in U-Boot's SPL upon
watchdog reset (e.g. running downstream L4T Linux kernel as there
exists no mainline Tegra20 watchdog driver as of yet).

The last patch in this series is not really related but just gets rid
of a spurious MAX_I2C_RETRY define in the Colibri T20's board file.


Marcel Ziswiler (3):
  arm: tegra20: implement early pmic rail configuration
  colibri_t20: enable early pmic rail configuration
  colibri_t20: get rid of spurious MAX_I2C_RETRY define

 arch/arm/mach-tegra/tegra20/cpu.c       | 76 ++++++++++++++++++++++++++++++++-
 board/toradex/colibri_t20/colibri_t20.c |  1 -
 include/configs/colibri_t20.h           |  2 +
 3 files changed, 77 insertions(+), 2 deletions(-)

-- 
2.4.3

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Stephen Warren]

On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
>
> Implement early TPS6586X PMIC rail configuration setting SM0 being
> VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
>
> While those are PMIC power-up defaults the SoC might have been reset
> separately with certain rails being left at lower DVFS states which
> is e.g. the case upon watchdog reset while otherwise nearly idling.

Is there any guarantee that the voltage levels are high enough for the 
AVP to run correctly before the CORE rail is adjusted? It sounds to me 
like a HW design issue; the SoC reset output should reset the PMIC too.

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Marcel Ziswiler]

On 20 Aug 2015 21:58, Stephen Warren <swarren@wwwdotorg.org> wrote:

> Is there any guarantee that the voltage levels are high enough for the
> AVP to run correctly before the CORE rail is adjusted? It sounds to me
> like a HW design issue; the SoC reset output should reset the PMIC too.

If by guarantee you mean whether it is impossible by software to completely screw the rail configuration no there is no such guarantee. But even on T30 where usually some PMIC GPIOs are used to switch to a sane default software could mess up the configuration of that as well. To prevent any of that I guess a higher level of trusted computing stuff would be required. At the end we just have to assume that regular DVFS operation should never leave it in a completely unbootable state.

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Stephen Warren]

On 08/20/2015 04:59 PM, Marcel Ziswiler wrote:
> On 20 Aug 2015 21:58, Stephen Warren <swarren@wwwdotorg.org> wrote:
>
>  > Is there any guarantee that the voltage levels are high enough for the
>  > AVP to run correctly before the CORE rail is adjusted? It sounds to me
>  > like a HW design issue; the SoC reset output should reset the PMIC too.
>
> If by guarantee you mean whether it is impossible by software to
> completely screw the rail configuration no there is no such guarantee.
> But even on T30 where usually some PMIC GPIOs are used to switch to a
> sane default software could mess up the configuration of that as well.
> To prevent any of that I guess a higher level of trusted computing stuff
> would be required. At the end we just have to assume that regular DVFS
> operation should never leave it in a completely unbootable state.

That almost sounds like there's no need for this patch/series then, 
since we're assuming that SW won't leave the HW in a bad state. If SW 
can leave HW in a bad state, the only choice is to fix the issue in HW. 
However, perhaps you mean there are some states that are worse than 
others; we assume that the rails required for the AVP are always in a 
good state but the rails required for the CPU/CCPLEX may not be?

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Marcel Ziswiler]

On 24 Aug 2015 18:25, Stephen Warren <swarren@wwwdotorg.org> wrote:

> That almost sounds like there's no need for this patch/series then,
> since we're assuming that SW won't leave the HW in a bad state.

Well, define bad state please.

> If SW
> can leave HW in a bad state, the only choice is to fix the issue in HW.

As mentioned before I don't quite agree.

> However, perhaps you mean there are some states that are worse than
> others; we assume that the rails required for the AVP are always in a
> good state but the rails required for the CPU/CCPLEX may not be?

No, at the end I'm just talking about regular DVFS operation. In fact the AVPs rail gets adjusted too however not in any way such that it won't operate any longer.