[U-Boot] [PATCH 2/3] colibri_t20: enable early pmic rail configuration

[U-Boot] [PATCH 2/3] colibri_t20: enable early pmic rail configuration

[Marcel Ziswiler]

On 20 Aug 2015 22:01, Stephen Warren <swarren@wwwdotorg.org> wrote:

> Rather than enable this with yet another CONFIG_ option, perhaps we can
> put this code into a C file dedicated to the colibri_t20 board, and then
> have the common code call it (and implement a weak function that does
> nothing to satisfy the linker on other boards).

I'm fine with that but during my initial investigation I noticed that there are at least 3 to 4 different ways how the early PMIC configuration could be realised just within the Tegra's and your proposal is not even one of them.

[U-Boot] [PATCH 2/3] colibri_t20: enable early pmic rail configuration

[Stephen Warren]

On 08/20/2015 05:13 PM, Marcel Ziswiler wrote:
> On 20 Aug 2015 22:01, Stephen Warren <swarren@wwwdotorg.org> wrote:
>
>  > Rather than enable this with yet another CONFIG_ option, perhaps we can
>  > put this code into a C file dedicated to the colibri_t20 board, and then
>  > have the common code call it (and implement a weak function that does
>  > nothing to satisfy the linker on other boards).
>
> I'm fine with that but during my initial investigation I noticed that
> there are at least 3 to 4 different ways how the early PMIC
> configuration could be realised just within the Tegra's and your
> proposal is not even one of them.

My proposal has nothing to do with how the PMIC code is implemented, 
simply where to invoke it. This ensures that board-specific code doesn't 
get dumped into core files.

[U-Boot] [PATCH 0/3] arm: tegra20/colibri_t20: early pmic rail configuration

[Marcel Ziswiler]

Implement early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.

While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.

This fixes an issue of the Colibri T20 being stuck in U-Boot's SPL upon
watchdog reset (e.g. running downstream L4T Linux kernel as there
exists no mainline Tegra20 watchdog driver as of yet).

The last patch in this series is not really related but just gets rid
of a spurious MAX_I2C_RETRY define in the Colibri T20's board file.


Marcel Ziswiler (3):
  arm: tegra20: implement early pmic rail configuration
  colibri_t20: enable early pmic rail configuration
  colibri_t20: get rid of spurious MAX_I2C_RETRY define

 arch/arm/mach-tegra/tegra20/cpu.c       | 76 ++++++++++++++++++++++++++++++++-
 board/toradex/colibri_t20/colibri_t20.c |  1 -
 include/configs/colibri_t20.h           |  2 +
 3 files changed, 77 insertions(+), 2 deletions(-)

-- 
2.4.3

[U-Boot] [PATCH 2/3] colibri_t20: enable early pmic rail configuration

[Marcel Ziswiler]

Enable early TPS6586X PMIC rail configuration setting SM0 being
VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.

While those are PMIC power-up defaults the SoC might have been reset
separately with certain rails being left at lower DVFS states which
is e.g. the case upon watchdog reset while otherwise nearly idling.

This fixes an issue being stuck in U-Boot's SPL upon watchdog reset
(e.g. running downstream L4T Linux kernel as there exists no mainline
Tegra20 watchdog driver as of yet).

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

 include/configs/colibri_t20.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 7611fc5..124d767 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -13,6 +13,8 @@
 
 #define CONFIG_ARCH_MISC_INIT
 
+#define CONFIG_TEGRA_EARLY_TPS6586X
+
 /* High-level configuration options */
 #define CONFIG_TEGRA_BOARD_STRING	"Toradex Colibri T20"
 
-- 
2.4.3

[U-Boot] [PATCH 2/3] colibri_t20: enable early pmic rail configuration

[Stephen Warren]

On 08/20/2015 01:52 AM, Marcel Ziswiler wrote:
> Enable early TPS6586X PMIC rail configuration setting SM0 being
> VDD_CORE_1.2V to 1.2 volts and SM1 being VDD_CPU_1.0V to 1.0 volts.
>
> While those are PMIC power-up defaults the SoC might have been reset
> separately with certain rails being left at lower DVFS states which
> is e.g. the case upon watchdog reset while otherwise nearly idling.
>
> This fixes an issue being stuck in U-Boot's SPL upon watchdog reset
> (e.g. running downstream L4T Linux kernel as there exists no mainline
> Tegra20 watchdog driver as of yet).

Rather than enable this with yet another CONFIG_ option, perhaps we can 
put this code into a C file dedicated to the colibri_t20 board, and then 
have the common code call it (and implement a weak function that does 
nothing to satisfy the linker on other boards).