[U-Boot] [PATCH v5 06/13] imx: system counter driver for imx7d and mx6ul

[Stefano Babic <sbabic@denx.de>]

On 25/08/2015 23:16, Alonso Adrian wrote:
> Hi Stefano,
> 
>> -----Original Message-----
>> From: Stefano Babic [mailto:sbabic at denx.de]
>> Sent: Sunday, August 23, 2015 11:07 AM
>> To: Alonso Lazcano Adrian-B38018 <aalonso@freescale.com>; u-
>> boot at lists.denx.de; sbabic at denx.de; Estevam Fabio-R49496
>> <Fabio.Estevam@freescale.com>
>> Cc: otavio at ossystems.com.br; Li Frank-B20596 <Frank.Li@freescale.com>;
>> Garg Nitin-B37173 <nitin.garg@freescale.com>
>> Subject: Re: [PATCH v5 06/13] imx: system counter driver for imx7d and mx6ul
>>
>> On 11/08/2015 18:19, Adrian Alonso wrote:
>>> * The system counter driver for imx7d abd mx6ul, move
>>>   this timer driver to imx-common and rename it as syscounter.c
>>>
>>>   For mx6ul and mx7, configurations are used for choose the GPT timer
>>>   or system counter timer (default).
>>>
>>>   GPT timer:              CONFIG_GPT_TIMER
>>>   System counter timer:   CONFIG_SYSCOUNTER_TIMER
>>
>> I am asking why system counter timer becomes default when all boards are
>> using GPT_TIMER. Should be not better to set GPT as default, and only a few
>> boards will set CONFIG_SYSCOUNTER_TIMER, even if configuration is
>> factorized in mx6_common.h ?
> [Adrian] The commit log description is a little confusing, what it should say is that
> SYSCOUNTER_TIMER is the default timer for iMX7 and iMX6UL.
>>
>>>
>>>   For mx6dqp GPT timer is the default setting.
>>>
>>> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
>>> Signed-off-by: Ye.Li <B37916@freescale.com>
>>> ---
>>> Changes for V2: Resend
>>> Changes for V3: Resend
>>> Changes for V4: Resend
>>> Changes for V5: Resend
>>>
>>>  arch/arm/imx-common/syscounter.c             | 126
>> +++++++++++++++++++++++++++
>>>  arch/arm/include/asm/imx-common/syscounter.h |  29 ++++++
>>>  include/configs/mx6_common.h                 |   1 +
>>>  3 files changed, 156 insertions(+)
>>>  create mode 100644 arch/arm/imx-common/syscounter.c  create mode
>>> 100644 arch/arm/include/asm/imx-common/syscounter.h
>>>
>>> diff --git a/arch/arm/imx-common/syscounter.c
>>> b/arch/arm/imx-common/syscounter.c
>>> new file mode 100644
>>> index 0000000..e00fef2
>>> --- /dev/null
>>> +++ b/arch/arm/imx-common/syscounter.c
>>> @@ -0,0 +1,126 @@
>>> +/*
>>> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
>>> + *
>>> + * SPDX-License-Identifier:	GPL-2.0+
>>> + *
>>> + * The file use ls102xa/timer.c as a reference.
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <div64.h>
>>> +#include <asm/arch/imx-regs.h>
>>> +#include <asm/arch/sys_proto.h>
>>> +#include <asm/imx-common/syscounter.h>
>>> +
>>> +DECLARE_GLOBAL_DATA_PTR;
>>> +
>>> +/*
>>> + * This function is intended for SHORT delays only.
>>> + * It will overflow at around 10 seconds @ 400MHz,
>>> + * or 20 seconds @ 200MHz.
>>> + */
>>> +unsigned long usec2ticks(unsigned long usec) {
>>> +	ulong ticks;
>>> +
>>> +	if (usec < 1000)
>>> +		ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
>>> +	else
>>> +		ticks = ((usec / 10) * (get_tbclk() / 100000));
>>> +
>>> +	return ticks;
>>> +}
>>> +
>>> +static inline unsigned long long tick_to_time(unsigned long long
>>> +tick) {
>>> +	unsigned long freq;
>>> +
>>> +	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
>>> +
>>> +	tick *= CONFIG_SYS_HZ;
>>> +	do_div(tick, freq);
>>> +
>>> +	return tick;
>>> +}
>>> +
>>> +static inline unsigned long long us_to_tick(unsigned long long usec)
>>> +{
>>> +	unsigned long freq;
>>> +
>>> +	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
>>> +
>>> +	usec = usec * freq  + 999999;
>>> +	do_div(usec, 1000000);
>>> +
>>> +	return usec;
>>> +}
>>> +
>>> +int timer_init(void)
>>> +{
>>> +	struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
>>> +	unsigned long val, freq;
>>> +
>>> +	freq = CONFIG_SC_TIMER_CLK;
>>> +	asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
>>> +
>>> +	writel(freq, &sctr->cntfid0);
>>> +
>>> +	/* Enable system counter */
>>> +	val = readl(&sctr->cntcr);
>>> +	val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
>>> +	val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
>>> +	writel(val, &sctr->cntcr);
>>> +
>>> +	gd->arch.tbl = 0;
>>> +	gd->arch.tbu = 0;
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +unsigned long long get_ticks(void)
>>> +{
>>> +	unsigned long long now;
>>> +
>>> +	asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
>>> +
>>> +	gd->arch.tbl = (unsigned long)(now & 0xffffffff);
>>> +	gd->arch.tbu = (unsigned long)(now >> 32);
>>> +
>>> +	return now;
>>> +}
>>> +
>>> +ulong get_timer_masked(void)
>>> +{
>>> +	return tick_to_time(get_ticks());
>>> +}
>>> +
>>> +ulong get_timer(ulong base)
>>> +{
>>> +	return get_timer_masked() - base;
>>> +}
>>> +
>>> +void __udelay(unsigned long usec)
>>> +{
>>> +	unsigned long long tmp;
>>> +	ulong tmo;
>>> +
>>> +	tmo = us_to_tick(usec);
>>> +	tmp = get_ticks() + tmo;	/* get current timestamp */
>>> +
>>> +	while (get_ticks() < tmp)	/* loop till event */
>>> +		 /*NOP*/;
>>> +}
>>> +
>>> +/*
>>> + * This function is derived from PowerPC code (timebase clock frequency).
>>> + * On ARM it returns the number of timer ticks per second.
>>> + */
>>> +ulong get_tbclk(void)
>>> +{
>>> +	unsigned long freq;
>>> +
>>> +	asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
>>> +
>>> +	return freq;
>>> +}
>>> diff --git a/arch/arm/include/asm/imx-common/syscounter.h
>>> b/arch/arm/include/asm/imx-common/syscounter.h
>>> new file mode 100644
>>> index 0000000..bdbe26c
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/imx-common/syscounter.h
>>> @@ -0,0 +1,29 @@
>>> +/*
>>> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
>>> + *
>>> + * SPDX-License-Identifier:	GPL-2.0+
>>> + */
>>> +
>>> +#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
>>> +#define _ASM_ARCH_SYSTEM_COUNTER_H
>>> +
>>> +/* System Counter */
>>> +struct sctr_regs {
>>> +	u32 cntcr;
>>> +	u32 cntsr;
>>> +	u32 cntcv1;
>>> +	u32 cntcv2;
>>> +	u32 resv1[4];
>>> +	u32 cntfid0;
>>> +	u32 cntfid1;
>>> +	u32 cntfid2;
>>> +	u32 resv2[1001];
>>> +	u32 counterid[1];
>>> +};
>>> +
>>> +#define SC_CNTCR_ENABLE		(1 << 0)
>>> +#define SC_CNTCR_HDBG		(1 << 1)
>>> +#define SC_CNTCR_FREQ0		(1 << 8)
>>> +#define SC_CNTCR_FREQ1		(1 << 9)
>>> +
>>> +#endif
>>> diff --git a/include/configs/mx6_common.h
>>> b/include/configs/mx6_common.h index ef4cb68..e26c814 100644
>>> --- a/include/configs/mx6_common.h
>>> +++ b/include/configs/mx6_common.h
>>> @@ -32,6 +32,7 @@
>>>  #endif
>>>  #define CONFIG_BOARD_POSTCLK_INIT
>>>  #define CONFIG_MXC_GPT_HCLK
>>> +#define CONFIG_GPT_TIMER
> [Adrian] I will drop this change in mx6_common.h and rearrange the arch/arm/imx-common/Makefile
> When introducing iMX7 SoC support to select the proper timer setting.


Ok, fine !

Regards,
Stefano Babic

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