[U-Boot] [PATCH 03/45] arm: Remove most LaCie boards

Simon Guinot
2015-08-31T07:51:18Z

On Sun, Aug 30, 2015 at 07:18:57PM -0600, Simon Glass wrote:
> These boards have not been converted to generic board by the deadline.
> Remove all except edmini_v2 (which has been converted).

Hi Simon,

Great... Is it still time to convert this boards to "generic board"
support ?

You know, a direct email (I mean with my email address in the To or Cc
fields) to make me aware of this project would have been both fair and
very appreciated.

Thanks,

Simon

>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> arch/arm/mach-kirkwood/Kconfig | 12 --
> board/LaCie/net2big_v2/Kconfig | 12 --
> board/LaCie/net2big_v2/MAINTAINERS | 11 --
> board/LaCie/net2big_v2/Makefile | 15 --
> board/LaCie/net2big_v2/kwbimage.cfg | 151 -----------------
> board/LaCie/net2big_v2/net2big_v2.c | 253 ----------------------------
> board/LaCie/net2big_v2/net2big_v2.h | 29 ----
> board/LaCie/netspace_v2/Kconfig | 12 --
> board/LaCie/netspace_v2/MAINTAINERS | 14 --
> board/LaCie/netspace_v2/Makefile | 12 --
> board/LaCie/netspace_v2/kwbimage-is2.cfg | 151 -----------------
> board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 151 -----------------
> board/LaCie/netspace_v2/kwbimage.cfg | 151 -----------------
> board/LaCie/netspace_v2/netspace_v2.c | 117 -------------
> board/LaCie/netspace_v2/netspace_v2.h | 23 ---
> board/LaCie/wireless_space/Kconfig | 12 --
> board/LaCie/wireless_space/MAINTAINERS | 6 -
> board/LaCie/wireless_space/Makefile | 12 --
> board/LaCie/wireless_space/kwbimage.cfg | 71 --------
> board/LaCie/wireless_space/wireless_space.c | 165 ------------------
> configs/net2big_v2_defconfig | 8 -
> configs/netspace_lite_v2_defconfig | 8 -
> configs/netspace_max_v2_defconfig | 8 -
> configs/netspace_mini_v2_defconfig | 8 -
> configs/netspace_v2_defconfig | 8 -
> configs/wireless_space_defconfig | 7 -
> include/configs/lacie_kw.h | 214 -----------------------
> include/configs/wireless_space.h | 179 --------------------
> 28 files changed, 1820 deletions(-)
> delete mode 100644 board/LaCie/net2big_v2/Kconfig
> delete mode 100644 board/LaCie/net2big_v2/MAINTAINERS
> delete mode 100644 board/LaCie/net2big_v2/Makefile
> delete mode 100644 board/LaCie/net2big_v2/kwbimage.cfg
> delete mode 100644 board/LaCie/net2big_v2/net2big_v2.c
> delete mode 100644 board/LaCie/net2big_v2/net2big_v2.h
> delete mode 100644 board/LaCie/netspace_v2/Kconfig
> delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS
> delete mode 100644 board/LaCie/netspace_v2/Makefile
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h
> delete mode 100644 board/LaCie/wireless_space/Kconfig
> delete mode 100644 board/LaCie/wireless_space/MAINTAINERS
> delete mode 100644 board/LaCie/wireless_space/Makefile
> delete mode 100644 board/LaCie/wireless_space/kwbimage.cfg
> delete mode 100644 board/LaCie/wireless_space/wireless_space.c
> delete mode 100644 configs/net2big_v2_defconfig
> delete mode 100644 configs/netspace_lite_v2_defconfig
> delete mode 100644 configs/netspace_max_v2_defconfig
> delete mode 100644 configs/netspace_mini_v2_defconfig
> delete mode 100644 configs/netspace_v2_defconfig
> delete mode 100644 configs/wireless_space_defconfig
> delete mode 100644 include/configs/lacie_kw.h
> delete mode 100644 include/configs/wireless_space.h
>
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index 1261885..1ac99b8 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -40,15 +40,6 @@ config TARGET_TK71
> config TARGET_KM_KIRKWOOD
> bool "KM_KIRKWOOD Board"
>
> -config TARGET_NET2BIG_V2
> - bool "LaCie 2Big Network v2 NAS Board"
> -
> -config TARGET_NETSPACE_V2
> - bool "LaCie netspace_v2 Board"
> -
> -config TARGET_WIRELESS_SPACE
> - bool "LaCie Wireless_space Board"
> -
> config TARGET_IB62X0
> bool "ib62x0 Board"
>
> @@ -78,9 +69,6 @@ source "board/d-link/dns325/Kconfig"
> source "board/iomega/iconnect/Kconfig"
> source "board/karo/tk71/Kconfig"
> source "board/keymile/km_arm/Kconfig"
> -source "board/LaCie/net2big_v2/Kconfig"
> -source "board/LaCie/netspace_v2/Kconfig"
> -source "board/LaCie/wireless_space/Kconfig"
> source "board/raidsonic/ib62x0/Kconfig"
> source "board/Seagate/dockstar/Kconfig"
> source "board/Seagate/goflexhome/Kconfig"
> diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig
> deleted file mode 100644
> index ba460db..0000000
> --- a/board/LaCie/net2big_v2/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_NET2BIG_V2
> -
> -config SYS_BOARD
> - default "net2big_v2"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "lacie_kw"
> -
> -endif
> diff --git a/board/LaCie/net2big_v2/MAINTAINERS b/board/LaCie/net2big_v2/MAINTAINERS
> deleted file mode 100644
> index 205c75e..0000000
> --- a/board/LaCie/net2big_v2/MAINTAINERS
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -NET2BIG_V2 BOARD
> -#M: -
> -S: Maintained
> -F: board/LaCie/net2big_v2/
> -F: include/configs/lacie_kw.h
> -F: configs/d2net_v2_defconfig
> -
> -NET2BIG_V2 BOARD
> -M: Simon Guinot <simon.guinot@sequanux.org>
> -S: Maintained
> -F: configs/net2big_v2_defconfig
> diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
> deleted file mode 100644
> index f3074af..0000000
> --- a/board/LaCie/net2big_v2/Makefile
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := net2big_v2.o ../common/common.o
> -ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
> -obj-y += ../common/cpld-gpio-bus.o
> -endif
> diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
> deleted file mode 100644
> index 453fcb2..0000000
> --- a/board/LaCie/net2big_v2/kwbimage.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000C30 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000CCCC # DDR Address Control
> -# bit1-0: 01, Cs0width=x16
> -# bit3-2: 11, Cs0size=1Gb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000662 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000044 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
> deleted file mode 100644
> index 263bb54..0000000
> --- a/board/LaCie/net2big_v2/net2big_v2.c
> +++ /dev/null
> @@ -1,253 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <i2c.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "net2big_v2.h"
> -#include "../common/common.h"
> -#include "../common/cpld-gpio-bus.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - /* GPIO configuration */
> - mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
> - NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - static const u32 kwmpp_config[] = {
> - MPP0_SPI_SCn,
> - MPP1_SPI_MOSI,
> - MPP2_SPI_SCK,
> - MPP3_SPI_MISO,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Request power-off */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP13_GPIO, /* Rear power switch (on|auto) */
> - MPP14_GPIO, /* USB fuse alarm */
> - MPP15_GPIO, /* Rear power switch (auto|off) */
> - MPP16_GPIO, /* SATA HDD1 power */
> - MPP17_GPIO, /* SATA HDD2 power */
> - MPP20_SATA1_ACTn,
> - MPP21_SATA0_ACTn,
> - MPP24_GPIO, /* USB mode select */
> - MPP26_GPIO, /* USB device vbus */
> - MPP28_GPIO, /* USB enable host vbus */
> - MPP29_GPIO, /* CPLD GPIO bus ALE */
> - MPP34_GPIO, /* Rear Push button 0=on 1=off */
> - MPP35_GPIO, /* Inhibit switch power-off */
> - MPP36_GPIO, /* SATA HDD1 presence */
> - MPP37_GPIO, /* SATA HDD2 presence */
> - MPP40_GPIO, /* eSATA presence */
> - MPP44_GPIO, /* CPLD GPIO bus (data 0) */
> - MPP45_GPIO, /* CPLD GPIO bus (data 1) */
> - MPP46_GPIO, /* CPLD GPIO bus (data 2) */
> - MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
> - MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
> - MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
> - 0
> - };
> -
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
> -/*
> - * Start I2C fan (GMT G762 controller)
> - */
> -static void init_fan(void)
> -{
> - u8 data;
> -
> - i2c_set_bus_num(0);
> -
> - /* Enable open-loop and PWM modes */
> - data = 0x20;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_FAN_CMD1, 1, &data, 1) != 0)
> - goto err;
> - data = 0;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_SET_CNT, 1, &data, 1) != 0)
> - goto err;
> - /*
> - * RPM to PWM (set_out register) fan speed conversion array:
> - * 0 0x00
> - * 1500 0x04
> - * 2800 0x08
> - * 3400 0x0C
> - * 3700 0x10
> - * 4400 0x20
> - * 4700 0x30
> - * 4800 0x50
> - * 5200 0x80
> - * 5400 0xC0
> - * 5500 0xFF
> - *
> - * Start fan at low speed (2800 RPM):
> - */
> - data = 0x08;
> - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
> - G762_REG_SET_OUT, 1, &data, 1) != 0)
> - goto err;
> -
> - return;
> -err:
> - printf("Error: failed to start I2C fan @%02x\n",
> - CONFIG_SYS_I2C_G762_ADDR);
> -}
> -#else
> -static void init_fan(void) {}
> -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
> -
> -#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
> -/*
> - * CPLD GPIO bus:
> - *
> - * - address register : bit [0-2] -> GPIO [47-49]
> - * - data register : bit [0-2] -> GPIO [44-46]
> - * - enable register : GPIO 29
> - */
> -static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
> -static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
> -
> -static struct cpld_gpio_bus cpld_gpio_bus = {
> - .addr = cpld_gpio_bus_addr,
> - .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
> - .data = cpld_gpio_bus_data,
> - .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
> - .enable = 29,
> -};
> -
> -/*
> - * LEDs configuration:
> - *
> - * The LEDs are controlled by a CPLD and can be configured through
> - * the CPLD GPIO bus.
> - *
> - * Address register selection:
> - *
> - * addr | register
> - * ----------------------------
> - * 0 | front LED
> - * 1 | front LED brightness
> - * 2 | SATA LED brightness
> - * 3 | SATA0 LED
> - * 4 | SATA1 LED
> - * 5 | SATA2 LED
> - * 6 | SATA3 LED
> - * 7 | SATA4 LED
> - *
> - * Data register configuration:
> - *
> - * data | LED brightness
> - * -------------------------------------------------
> - * 0 | min (off)
> - * - | -
> - * 7 | max
> - *
> - * data | front LED mode
> - * -------------------------------------------------
> - * 0 | fix off
> - * 1 | fix blue on
> - * 2 | fix red on
> - * 3 | blink blue on=1 sec and blue off=1 sec
> - * 4 | blink red on=1 sec and red off=1 sec
> - * 5 | blink blue on=2.5 sec and red on=0.5 sec
> - * 6 | blink blue on=1 sec and red on=1 sec
> - * 7 | blink blue on=0.5 sec and blue off=2.5 sec
> - *
> - * data | SATA LED mode
> - * -------------------------------------------------
> - * 0 | fix off
> - * 1 | SATA activity blink
> - * 2 | fix red on
> - * 3 | blink blue on=1 sec and blue off=1 sec
> - * 4 | blink red on=1 sec and red off=1 sec
> - * 5 | blink blue on=2.5 sec and red on=0.5 sec
> - * 6 | blink blue on=1 sec and red on=1 sec
> - * 7 | fix blue on
> - */
> -static void init_leds(void)
> -{
> - /* Enable the front blue LED */
> - cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
> -
> - /* Configure SATA LEDs to blink in relation with the SATA activity */
> - cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
> - cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
> -}
> -#else
> -static void init_leds(void) {}
> -#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
> -
> -int misc_init_r(void)
> -{
> - init_fan();
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - init_leds();
> -
> - return 0;
> -}
> -#endif /* CONFIG_MISC_INIT_R */
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> - mv_phy_88e1116_init("egiga0", 8);
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO)
> -/* Return GPIO push button status */
> -static int
> -do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
> -}
> -
> -U_BOOT_CMD(button, 1, 1, do_read_push_button,
> - "Return GPIO push button status 0=off 1=on", "");
> -#endif
> diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
> deleted file mode 100644
> index 8dead89..0000000
> --- a/board/LaCie/net2big_v2/net2big_v2.h
> +++ /dev/null
> @@ -1,29 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef NET2BIG_V2_H
> -#define NET2BIG_V2_H
> -
> -/* GPIO configuration */
> -#define NET2BIG_V2_OE_LOW 0x0600E000
> -#define NET2BIG_V2_OE_HIGH 0x00000134
> -#define NET2BIG_V2_OE_VAL_LOW 0x10030000
> -#define NET2BIG_V2_OE_VAL_HIGH 0x00000000
> -
> -/* Buttons */
> -#define NET2BIG_V2_GPIO_PUSH_BUTTON 34
> -
> -/* GMT G762 registers (I2C fan controller) */
> -#define G762_REG_SET_CNT 0x00
> -#define G762_REG_SET_OUT 0x03
> -#define G762_REG_FAN_CMD1 0x04
> -
> -#endif /* NET2BIG_V2_H */
> diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
> deleted file mode 100644
> index 930b822..0000000
> --- a/board/LaCie/netspace_v2/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_NETSPACE_V2
> -
> -config SYS_BOARD
> - default "netspace_v2"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "lacie_kw"
> -
> -endif
> diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
> deleted file mode 100644
> index 55fd50d..0000000
> --- a/board/LaCie/netspace_v2/MAINTAINERS
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -NETSPACE_V2 BOARD
> -M: Simon Guinot <simon.guinot@sequanux.org>
> -S: Maintained
> -F: board/LaCie/netspace_v2/
> -F: include/configs/lacie_kw.h
> -F: configs/inetspace_v2_defconfig
> -F: configs/netspace_max_v2_defconfig
> -F: configs/netspace_v2_defconfig
> -
> -NETSPACE_LITE_V2 BOARD
> -#M: -
> -S: Maintained
> -F: configs/netspace_lite_v2_defconfig
> -F: configs/netspace_mini_v2_defconfig
> diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
> deleted file mode 100644
> index 47778d8..0000000
> --- a/board/LaCie/netspace_v2/Makefile
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := netspace_v2.o ../common/common.o
> diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
> deleted file mode 100644
> index 98713ea..0000000
> --- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x00000008 # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> deleted file mode 100644
> index 6b32193..0000000
> --- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000DDDD # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
> deleted file mode 100644
> index 1515f81..0000000
> --- a/board/LaCie/netspace_v2/kwbimage.cfg
> +++ /dev/null
> @@ -1,151 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000000C # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 11, Cs0size=1Gb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
> deleted file mode 100644
> index 17e6296..0000000
> --- a/board/LaCie/netspace_v2/netspace_v2.c
> +++ /dev/null
> @@ -1,117 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "netspace_v2.h"
> -#include "../common/common.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - /* Gpio configuration */
> - mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
> - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - static const u32 kwmpp_config[] = {
> - MPP0_SPI_SCn,
> - MPP1_SPI_MOSI,
> - MPP2_SPI_SCK,
> - MPP3_SPI_MISO,
> - MPP4_NF_IO6,
> - MPP5_NF_IO7,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Fan speed (bit 1) */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP12_GPO, /* Red led */
> - MPP14_GPIO, /* USB fuse */
> - MPP16_GPIO, /* SATA 0 power */
> - MPP17_GPIO, /* SATA 1 power */
> - MPP18_NF_IO0,
> - MPP19_NF_IO1,
> - MPP20_SATA1_ACTn,
> - MPP21_SATA0_ACTn,
> - MPP22_GPIO, /* Fan speed (bit 0) */
> - MPP23_GPIO, /* Fan power */
> - MPP24_GPIO, /* USB mode select */
> - MPP25_GPIO, /* Fan rotation fail */
> - MPP26_GPIO, /* USB vbus-in detection */
> - MPP28_GPIO, /* USB enable vbus-out */
> - MPP29_GPIO, /* Blue led (slow register) */
> - MPP30_GPIO, /* Blue led (command register) */
> - MPP31_GPIO, /* Board power off */
> - MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
> - MPP33_GPIO, /* Fan speed (bit 2) */
> - 0
> - };
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -int misc_init_r(void)
> -{
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> - mv_phy_88e1318_init("egiga0", 0);
> -#else
> - mv_phy_88e1116_init("egiga0", 8);
> -#endif
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO)
> -/* Return GPIO button status */
> -static int
> -do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
> -}
> -
> -U_BOOT_CMD(button, 1, 1, do_read_button,
> - "Return GPIO button status 0=off 1=on", "");
> -#endif
> diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h
> deleted file mode 100644
> index cdf5238..0000000
> --- a/board/LaCie/netspace_v2/netspace_v2.h
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef NETSPACE_V2_H
> -#define NETSPACE_V2_H
> -
> -/* GPIO configuration */
> -#define NETSPACE_V2_OE_LOW 0x06004000
> -#define NETSPACE_V2_OE_HIGH 0x00000031
> -#define NETSPACE_V2_OE_VAL_LOW 0x10030000
> -#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
> -
> -#define NETSPACE_V2_GPIO_BUTTON 32
> -
> -#endif /* NETSPACE_V2_H */
> diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig
> deleted file mode 100644
> index 75a2fc5..0000000
> --- a/board/LaCie/wireless_space/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_WIRELESS_SPACE
> -
> -config SYS_BOARD
> - default "wireless_space"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "wireless_space"
> -
> -endif
> diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS
> deleted file mode 100644
> index c32ecb8..0000000
> --- a/board/LaCie/wireless_space/MAINTAINERS
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -WIRELESS_SPACE BOARD
> -M: Albert ARIBAUD <albert.u.boot@aribaud.net>
> -S: Maintained
> -F: board/LaCie/wireless_space/
> -F: include/configs/wireless_space.h
> -F: configs/wireless_space_defconfig
> diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
> deleted file mode 100644
> index 90a84f4..0000000
> --- a/board/LaCie/wireless_space/Makefile
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -
> -obj-y := wireless_space.o ../common/common.o
> diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
> deleted file mode 100644
> index 037248b..0000000
> --- a/board/LaCie/wireless_space/kwbimage.cfg
> +++ /dev/null
> @@ -1,71 +0,0 @@
> -#
> -# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
> -#
> -# Based on netspace_v2 kwbimage.cfg:
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -#
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM nand # Boot from NAND flash
> -NAND_PAGE_SIZE 800
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Values taken from image original LaCie U-Boot header dump!
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000c30 # DDR Configuration register
> -
> -DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -
> -DATA 0xFFD01410 0x0000CCCC # DDR Address Control
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -
> -DATA 0xFFD0141C 0x00000662 # DDR Mode
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -
> -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
> -
> -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -DATA 0xFFD20134 0x66666666
> -DATA 0xFFD20138 0x66666666
> -DATA 0xFFD10000 0x01112222
> -DATA 0xFFD1000C 0x00000000
> -DATA 0xFFD10104 0x00000000
> -DATA 0xFFD10100 0x40000000
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
> deleted file mode 100644
> index 8620e4b..0000000
> --- a/board/LaCie/wireless_space/wireless_space.c
> +++ /dev/null
> @@ -1,165 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "../common/common.h"
> -#include "netdev.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -/* GPIO configuration: start FAN at low speed, USB and HDD */
> -
> -#define WIRELESS_SPACE_OE_LOW 0xFF006808
> -#define WIRELESS_SPACE_OE_HIGH 0x0000F989
> -#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080
> -#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240
> -
> -#define WIRELESS_SPACE_REAR_BUTTON 13
> -#define WIRELESS_SPACE_FRONT_BUTTON 43
> -
> -const u32 kwmpp_config[] = {
> - MPP0_NF_IO2,
> - MPP1_NF_IO3,
> - MPP2_NF_IO4,
> - MPP3_NF_IO5,
> - MPP4_NF_IO6,
> - MPP5_NF_IO7,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Fan speed (bit 1) */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP13_GPIO, /* Red led */
> - MPP14_GPIO, /* USB fuse */
> - MPP15_SATA0_ACTn,
> - MPP16_GPIO, /* SATA 0 power */
> - MPP17_GPIO, /* SATA 1 power */
> - MPP18_NF_IO0,
> - MPP19_NF_IO1,
> - MPP20_GE1_0, /* Gigabit Ethernet 1 */
> - MPP21_GE1_1,
> - MPP22_GE1_2,
> - MPP23_GE1_3,
> - MPP24_GE1_4,
> - MPP25_GE1_5,
> - MPP26_GE1_6,
> - MPP27_GE1_7,
> - MPP28_GE1_8,
> - MPP29_GE1_9,
> - MPP30_GE1_10,
> - MPP31_GE1_11,
> - MPP32_GE1_12,
> - MPP33_GE1_13,
> - MPP34_GE1_14,
> - MPP35_GE1_15,
> - MPP36_GPIO, /* Fan speed (bit 2) */
> - MPP37_GPIO, /* Fan speed (bit 0) */
> - MPP38_GPIO, /* Fan power */
> - MPP39_GPIO, /* Fan rotation fail */
> - MPP40_GPIO, /* Ethernet switch link */
> - MPP41_GPIO, /* USB enable host vbus */
> - MPP42_GPIO, /* LED clock control */
> - MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */
> - MPP44_GPIO, /* Red LED on/off */
> - MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */
> - MPP46_GPIO, /* Green LED on/off */
> - MPP47_GPIO, /* LED (blue, green) SATA activity blink */
> - MPP48_GPIO, /* Blue LED on/off */
> - 0
> -};
> -
> -struct mv88e61xx_config swcfg = {
> - .name = "egiga0",
> - .vlancfg = MV88E61XX_VLANCFG_ROUTER,
> - .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
> - .led_init = MV88E61XX_LED_INIT_EN,
> - .mdip = MV88E61XX_MDIP_NOCHANGE,
> - .portstate = MV88E61XX_PORTSTT_FORWARDING,
> - .cpuport = 0x20,
> - .ports_enabled = 0x3F,
> -};
> -
> -int board_early_init_f(void)
> -{
> - /* Gpio configuration */
> - mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
> - WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -int misc_init_r(void)
> -{
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!getenv("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_setenv_enetaddr("ethaddr", mac);
> - }
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> - /* configure switch on egiga0 */
> - mv88e61xx_switch_initialize(&swcfg);
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
> -/* Return GPIO button status */
> -static int
> -do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> -{
> - if (strcmp(argv[1], "button") == 0) {
> - if (strcmp(argv[2], "rear") == 0)
> - /* invert GPIO result for intuitive while/until use */
> - return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
> - else if (strcmp(argv[2], "front") == 0)
> - return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
> - else
> - return -1;
> - } else {
> - return -1;
> - }
> -}
> -
> -U_BOOT_CMD(ws, 3, 0, do_ws,
> - "Return GPIO button status 0=off 1=on",
> - "- ws button rear|front: test buttons' states\n"
> -);
> -#endif
> diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
> deleted file mode 100644
> index 09df520..0000000
> --- a/configs/net2big_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NET2BIG_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
> deleted file mode 100644
> index 862a9ae..0000000
> --- a/configs/netspace_lite_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
> deleted file mode 100644
> index 1829995..0000000
> --- a/configs/netspace_max_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
> deleted file mode 100644
> index 35cb154..0000000
> --- a/configs/netspace_mini_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
> deleted file mode 100644
> index a13452b..0000000
> --- a/configs/netspace_v2_defconfig
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_SPI_FLASH=y
> diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig
> deleted file mode 100644
> index 63013f6..0000000
> --- a/configs/wireless_space_defconfig
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_KIRKWOOD=y
> -CONFIG_TARGET_WIRELESS_SPACE=y
> -# CONFIG_CMD_IMLS is not set
> -# CONFIG_CMD_FLASH is not set
> -# CONFIG_CMD_SETEXPR is not set
> -ONFIG_SYS_PROMPT="ws> "
> diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
> deleted file mode 100644
> index 30810d3..0000000
> --- a/include/configs/lacie_kw.h
> +++ /dev/null
> @@ -1,214 +0,0 @@
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef _CONFIG_LACIE_KW_H
> -#define _CONFIG_LACIE_KW_H
> -
> -/*
> - * Machine number definition
> - */
> -#if defined(CONFIG_INETSPACE_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
> -#define CONFIG_IDENT_STRING " IS v2"
> -#elif defined(CONFIG_NETSPACE_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
> -#define CONFIG_IDENT_STRING " NS v2"
> -#elif defined(CONFIG_NETSPACE_LITE_V2)
> -#define MACH_TYPE_NETSPACE_LITE_V2 2983 /* missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2
> -#define CONFIG_IDENT_STRING " NS v2 Lite"
> -#elif defined(CONFIG_NETSPACE_MINI_V2)
> -#define MACH_TYPE_NETSPACE_MINI_V2 2831 /* missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2
> -#define CONFIG_IDENT_STRING " NS v2 Mini"
> -#elif defined(CONFIG_NETSPACE_MAX_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
> -#define CONFIG_IDENT_STRING " NS Max v2"
> -#elif defined(CONFIG_D2NET_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2
> -#define CONFIG_IDENT_STRING " D2 v2"
> -#elif defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
> -#define CONFIG_IDENT_STRING " 2Big v2"
> -#else
> -#error "Unknown board"
> -#endif
> -
> -/*
> - * High Level Configuration Options (easy to change)
> - */
> -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
> -/* SoC name */
> -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> -#define CONFIG_KW88F6192
> -#else
> -#define CONFIG_KW88F6281
> -#endif
> -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
> -
> -/*
> - * Commands configuration
> - */
> -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
> -#define CONFIG_CMD_ENV
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_SF
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IDE
> -#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
> -#define CONFIG_CMD_USB
> -#endif
> -
> -/*
> - * Core clock definition
> - */
> -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
> -
> -/*
> - * SDRAM configuration
> - */
> -#define CONFIG_NR_DRAM_BANKS 1
> -
> -/*
> - * Different SDRAM configuration and size for some of the boards derived
> - * from the Network Space v2
> - */
> -#if defined(CONFIG_INETSPACE_V2)
> -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
> -#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
> -#endif
> -
> -/*
> - * mv-common.h should be defined after CMD configs since it used them
> - * to enable certain macros
> - */
> -#include "mv-common.h"
> -
> -/* Remove or override few declarations from mv-common.h */
> -#undef CONFIG_RBTREE
> -#undef CONFIG_ENV_SPI_MAX_HZ
> -#undef CONFIG_SYS_IDE_MAXBUS
> -#undef CONFIG_SYS_IDE_MAXDEVICE
> -#undef CONFIG_SYS_PROMPT
> -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
> -#define CONFIG_SYS_IDE_MAXBUS 1
> -#define CONFIG_SYS_IDE_MAXDEVICE 1
> -#if defined(CONFIG_D2NET_V2)
> -#define CONFIG_SYS_PROMPT "d2v2> "
> -#elif defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_PROMPT "2big2> "
> -#else
> -#define CONFIG_SYS_PROMPT "ns2> "
> -#endif
> -
> -/*
> - * Enable platform initialisation via misc_init_r() function
> - */
> -#define CONFIG_MISC_INIT_R
> -
> -/*
> - * Ethernet Driver configuration
> - */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
> -#define CONFIG_NETCONSOLE
> -#endif
> -
> -/*
> - * SATA Driver configuration
> - */
> -#ifdef CONFIG_MVSATA_IDE
> -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
> -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
> - defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
> -#endif
> -#endif /* CONFIG_MVSATA_IDE */
> -
> -/*
> - * Enable GPI0 support
> - */
> -#define CONFIG_KIRKWOOD_GPIO
> -
> -/*
> - * Enable I2C support
> - */
> -#ifdef CONFIG_CMD_I2C
> -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
> -#define CONFIG_CMD_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
> -#if defined(CONFIG_NET2BIG_V2)
> -#define CONFIG_SYS_I2C_G762_ADDR 0x3e
> -#endif
> -#endif /* CONFIG_CMD_I2C */
> -
> -/*
> - * Partition support
> - */
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_EFI_PARTITION
> -
> -/*
> - * File systems support
> - */
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -
> -/*
> - * Use the HUSH parser
> - */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/*
> - * Console configuration
> - */
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -
> -/*
> - * Enable device tree support
> - */
> -#define CONFIG_OF_LIBFDT
> -
> -/*
> - * Environment variables configurations
> - */
> -#define CONFIG_ENV_IS_IN_SPI_FLASH
> -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
> -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
> -#define CONFIG_ENV_ADDR 0x70000
> -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
> -
> -/*
> - * Default environment variables
> - */
> -#define CONFIG_BOOTARGS "console=ttyS0,115200"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "dhcp && run netconsole; " \
> - "if run usbload || run diskload; then bootm; fi"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "stdin=serial\0" \
> - "stdout=serial\0" \
> - "stderr=serial\0" \
> - "bootfile=uImage\0" \
> - "loadaddr=0x800000\0" \
> - "autoload=no\0" \
> - "netconsole=" \
> - "set stdin $stdin,nc; " \
> - "set stdout $stdout,nc; " \
> - "set stderr $stderr,nc;\0" \
> - "diskload=ide reset && " \
> - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
> - "usbload=usb start && " \
> - "fatload usb 0:1 $loadaddr /boot/$bootfile\0"
> -
> -#endif /* _CONFIG_LACIE_KW_H */
> diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h
> deleted file mode 100644
> index 191ac1b..0000000
> --- a/include/configs/wireless_space.h
> +++ /dev/null
> @@ -1,179 +0,0 @@
> -/*
> - * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
> - *
> - * Based on the netspace_v2 code which is
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * SPDX-License-Identifier: GPL-2.0+
> - */
> -
> -#ifndef _CONFIG_WIRELESS_SPACE_H
> -#define _CONFIG_WIRELESS_SPACE_H
> -
> -/*
> - * Machine number definition
> - */
> -#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */
> -#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE
> -#define CONFIG_IDENT_STRING " Wireless Space"
> -
> -/*
> - * High Level Configuration Options (easy to change)
> - */
> -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
> -/* SoC name */
> -#define CONFIG_KW88F6281
> -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
> -
> -/*
> - * Commands configuration
> - */
> -#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */
> -#define CONFIG_CMD_ENV
> -#define CONFIG_CMD_DHCP
> -#define CONFIG_CMD_PING
> -#define CONFIG_CMD_NAND
> -#define CONFIG_CMD_I2C
> -#define CONFIG_CMD_IDE
> -#define CONFIG_CMD_USB
> -
> -/*
> - * Core clock definition
> - */
> -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
> -
> -/*
> - * SDRAM configuration
> - */
> -#define CONFIG_NR_DRAM_BANKS 1
> -
> -/*
> - * Different SDRAM configuration and size for some of the boards derived
> - * from the Network Space v2
> - */
> -
> -/*
> - * mv-common.h should be defined after CMD configs since it used them
> - * to enable certain macros
> - */
> -#include "mv-common.h"
> -
> -/* Remove or override few declarations from mv-common.h */
> -#undef CONFIG_RBTREE
> -#undef CONFIG_SYS_IDE_MAXBUS
> -#undef CONFIG_SYS_IDE_MAXDEVICE
> -#define CONFIG_SYS_IDE_MAXBUS 1
> -#define CONFIG_SYS_IDE_MAXDEVICE 1
> -
> -/*
> - * Ethernet Driver configuration
> - */
> -#ifdef CONFIG_CMD_NET
> -#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
> -#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */
> -#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
> -#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */
> -#define CONFIG_MII
> -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
> -#define CONFIG_NETCONSOLE
> -#define CONFIG_MV88E61XX_SWITCH
> -#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
> -#define CONFIG_MV88E61XX_CMD
> -#define CONFIG_CMD_TFTPPUT
> -#endif /* CONFIG_CMD_NET */
> -
> -/*
> - * SATA Driver configuration
> - */
> -#ifdef CONFIG_MVSATA_IDE
> -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
> -#endif /* CONFIG_MVSATA_IDE */
> -
> -/*
> - * Enable GPI0 support
> - */
> -#define CONFIG_KIRKWOOD_GPIO
> -
> -/*
> - * Enable I2C support
> - */
> -#ifdef CONFIG_CMD_I2C
> -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
> -#define CONFIG_CMD_EEPROM
> -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
> -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
> -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
> -#endif /* CONFIG_CMD_I2C */
> -
> -/*
> - * Partition support
> - */
> -#define CONFIG_DOS_PARTITION
> -#define CONFIG_EFI_PARTITION
> -
> -/*
> - * File systems support
> - */
> -#define CONFIG_CMD_EXT2
> -#define CONFIG_CMD_FAT
> -
> -/*
> - * Use the HUSH parser
> - */
> -#define CONFIG_SYS_HUSH_PARSER
> -
> -/*
> - * Console configuration
> - */
> -#define CONFIG_CONSOLE_MUX
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
> -
> -/*
> - * Enable device tree support
> - */
> -#define CONFIG_OF_LIBFDT
> -
> -/*
> - * Environment variables configurations
> - */
> -
> -#define CONFIG_ENV_IS_IN_NAND
> -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */
> -#define CONFIG_ENV_SIZE 0x20000 /* 128KB */
> -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */
> -
> -/*
> - * Board-specific command to make using buttons etc easier
> - */
> -
> -#define CONFIG_WIRELESS_SPACE_CMD
> -
> -/*
> - * Default environment variables
> - */
> -#define CONFIG_PREBOOT
> -
> -#define CONFIG_BOOTARGS "console=ttyS0,115200"
> -
> -#define CONFIG_BOOTCOMMAND \
> - "if run usbload || run diskload; then bootm; fi"
> -
> -#define CONFIG_EXTRA_ENV_SETTINGS \
> - "stdin=serial\0" \
> - "stdout=serial\0" \
> - "stderr=serial\0" \
> - "bootfile=uImage\0" \
> - "loadaddr=0x800000\0" \
> - "autoload=no\0" \
> - "netconsole=" \
> - "set stdin $stdin,nc; " \
> - "set stdout $stdout,nc; " \
> - "set stderr $stderr,nc;\0" \
> - "diskload=ide reset && " \
> - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
> - "usbload=usb start && " \
> - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \
> - "preboot=" \
> - "dhcp && run netconsole\0"
> -
> -#endif /* _CONFIG_WIRELESS_SPACE_H */
> --
> 2.5.0.457.gab17608
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