From mboxrd@z Thu Jan  1 00:00:00 1970
From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 1 Sep 2015 11:00:26 +0200
Subject: [U-Boot] [PATCH v4 07/16] dts: zc770-xm010: Enable zynq qspi
 controller node
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 <55E5605B.6030306@xilinx.com>
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On 09/01/2015 10:43 AM, Jagan Teki wrote:
> On 1 September 2015 at 13:52, Michal Simek <michal.simek@xilinx.com> wrote:
>> On 09/01/2015 08:11 AM, Jagan Teki wrote:
>>> Enabled zynq qspi controller node for zc770-xm010 board.
>>>
>>> => sf probe 0 -- bus0 for selecting spi controller
>>> => sf probe 1 -- bus1 for selecting qspi controller
>>>
>>> Signed-off-by: Jagan Teki <jteki@openedev.com>
>>> Cc: Simon Glass <sjg@chromium.org>
>>> Cc: Michal Simek <michal.simek@xilinx.com>
>>> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
>>> ---
>>>  arch/arm/dts/zynq-zc770-xm010.dts | 5 +++++
>>>  1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
>>> index 680f24c..eec4c96 100644
>>> --- a/arch/arm/dts/zynq-zc770-xm010.dts
>>> +++ b/arch/arm/dts/zynq-zc770-xm010.dts
>>> @@ -17,6 +17,7 @@
>>>               i2c0 = &i2c0;
>>>               serial0 = &uart1;
>>>               spi0 = &spi1;
>>> +             spi1 = &qspi;
>>
>> We have discussed this internally 2 weeks ago and I would prefer to have
>> spi0 = &gspi; because then we can better handle internal commands where
> 
> It is &qspi right not &gqspi

it is zynq that's why qspi.

Thanks,
Michal