[U-Boot] [PATCH] Fix FSL DDR clock adjust calculation.

[York Sun <yorksun@freescale.com>]

On 09/02/2015 09:31 AM, Joakim Tjernlund wrote:
> On Wed, 2015-09-02 at 08:35 -0500, York Sun wrote:
>>
>> On 09/02/2015 06:41 AM, Joakim Tjernlund wrote:
>>> T1040 RM specifies CLK_ADJUST as 5 bits starting at bit pos 9
>>> in DDR_DDR_SDRAM_CLK_CNTL, update code to match.
>>>
>>> Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
>>> ---
>>>  drivers/ddr/fsl/ctrl_regs.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
>>> index 3919257..57077e1 100644
>>> --- a/drivers/ddr/fsl/ctrl_regs.c
>>> +++ b/drivers/ddr/fsl/ctrl_regs.c
>>> @@ -1756,7 +1756,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
>>>  	clk_adjust = popts->clk_adjust;
>>>  	ddr->ddr_sdram_clk_cntl = (0
>>>  				   | ((ss_en & 0x1) << 31)
>>> -				   | ((clk_adjust & 0xF) << 23)
>>> +				   | ((clk_adjust & 0x1F) << 22)
>>>  				   );
>>>  	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
>>>  }
>>>
>>
>> NACK. This is logically correct but it needs to consider all DDR controllers.
>> Older controllers don't have the same bits for this field. So far we don't have
>> to use this this fine granularity on clock adjustment.
> 
> I have no idea what older controllers do with these bits so I leave it to you to find out.
> 
> Anyhow, current code is broken as the programmed value is doubled(we see this on our board
> which cannot boot linux without this fix)

Jocke,

Can you refer to Freescale board? You may be using correct clk_adjust value on
your board. But when you use this driver, you may have to adjust the value by
shifting 1 bit. You will lose some values but we haven't found it difficult.
This value is important but can also tolerate a wide range.

York