[U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500

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* [U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500
@ 2015-08-17 20:31 York Sun
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards York Sun
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram York Sun
  0 siblings, 2 replies; 5+ messages in thread
From: York Sun @ 2015-08-17 20:31 UTC (permalink / raw)
  To: u-boot

We have been using locked cache for init_ram for MPC85xx for quite a long
time. It works until e6500 comes. On e6500, L1 cache is write-through. L2
cache has to be enabled to hold the data. We have not locked L2 cache and
we used reserved space in ccsr to make the address valid. Now the reserved
address is no longer reserved, causing overlapping with SerDes module.
The first patch changes the physical address of init_ram for e6500 and
e5500 to another reserved space to avoid overlapping. The second patch
locks L2 cache instead of L1 cache for e6500.

York Sun (2):
  powerpc: configs: Fix init_ram physical address for several boards
  powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram

 arch/powerpc/cpu/mpc85xx/start.S |   10 +++++++++-
 include/configs/B4860QDS.h       |    4 ++--
 include/configs/T102xQDS.h       |    4 ++--
 include/configs/T102xRDB.h       |    4 ++--
 include/configs/T1040QDS.h       |    2 +-
 include/configs/T104xRDB.h       |    2 +-
 include/configs/T208xQDS.h       |    2 +-
 include/configs/T208xRDB.h       |    2 +-
 include/configs/T4240RDB.h       |    2 +-
 include/configs/t4qds.h          |    2 +-
 10 files changed, 21 insertions(+), 13 deletions(-)

-- 
1.7.9.5

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards
  2015-08-17 20:31 [U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500 York Sun
@ 2015-08-17 20:31 ` York Sun
  2015-09-02 15:22   ` York Sun
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram York Sun
  1 sibling, 1 reply; 5+ messages in thread
From: York Sun @ 2015-08-17 20:31 UTC (permalink / raw)
  To: u-boot

For e6500 and e5500 SoCs, it was intended to put init_ram address in
ccsr reserved space. It is no longer true since SerDes module took the
space. Move it to another reserved space at CCSR + 0x03c000.

Signed-off-by: York Sun <yorksun@freescale.com>
---

 include/configs/B4860QDS.h |    4 ++--
 include/configs/T102xQDS.h |    4 ++--
 include/configs/T102xRDB.h |    4 ++--
 include/configs/T1040QDS.h |    2 +-
 include/configs/T104xRDB.h |    2 +-
 include/configs/T208xQDS.h |    2 +-
 include/configs/T208xRDB.h |    2 +-
 include/configs/T4240RDB.h |    2 +-
 include/configs/t4qds.h    |    2 +-
 9 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 2bac68d..17cac18 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -460,13 +460,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 21a918a..f253325 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -475,13 +475,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 242c239..d94e07e 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -476,13 +476,13 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #else
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 #endif
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index af7d9f8..b7291d3 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -380,7 +380,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 8c7c573..2447792 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -432,7 +432,7 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b0ee0de..31f17a2 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -430,7 +430,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 8c637c2..000c9e1 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -390,7 +390,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 8ed6bf7..c66701b 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -179,7 +179,7 @@
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 658f8b2..e75a0d8 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -123,7 +123,7 @@
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards York Sun
@ 2015-09-02 15:22   ` York Sun
  0 siblings, 0 replies; 5+ messages in thread
From: York Sun @ 2015-09-02 15:22 UTC (permalink / raw)
  To: u-boot



On 08/17/2015 03:31 PM, York Sun wrote:
> For e6500 and e5500 SoCs, it was intended to put init_ram address in
> ccsr reserved space. It is no longer true since SerDes module took the
> space. Move it to another reserved space at CCSR + 0x03c000.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---

Applied to u-boot-mpc85xx master. Awaiting upstream.

York

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
  2015-08-17 20:31 [U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500 York Sun
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards York Sun
@ 2015-08-17 20:31 ` York Sun
  2015-09-02 15:22   ` York Sun
  1 sibling, 1 reply; 5+ messages in thread
From: York Sun @ 2015-08-17 20:31 UTC (permalink / raw)
  To: u-boot

MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>

---

 arch/powerpc/cpu/mpc85xx/start.S |   10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index a70fb71..d867e2a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1116,7 +1116,11 @@ switch_as:
 	li	r0,0
 1:
 	dcbz	r0,r3
-	dcbtls	0,r0,r3
+#ifdef CONFIG_E6500	/* Lock/unlock L2 cache instead of L1 */
+	dcbtls	2, r0, r3
+#else
+	dcbtls	0, r0, r3
+#endif
 	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
 	bdnz	1b
 
@@ -1727,7 +1731,11 @@ unlock_ram_in_cache:
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
 1:	dcbi	r0,r3
+#ifdef CONFIG_E6500	/* lock/unlock L2 cache instead of L1 */
+	dcblc	2, r0, r3
+#else
 	dcblc	r0,r3
+#endif
 	addi	r3,r3,CONFIG_SYS_CACHELINE_SIZE
 	bdnz	1b
 	sync
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram
  2015-08-17 20:31 ` [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram York Sun
@ 2015-09-02 15:22   ` York Sun
  0 siblings, 0 replies; 5+ messages in thread
From: York Sun @ 2015-09-02 15:22 UTC (permalink / raw)
  To: u-boot



On 08/17/2015 03:31 PM, York Sun wrote:
> MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
> through cache on E6500. L2 cache is enabled to to hold the data. This
> patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
> 
> ---

Applied to u-boot-mpc85xx master. Awaiting upstream.

York

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2015-09-02 15:22 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-08-17 20:31 [U-Boot] [PATCH v1 0/2] Fix init_ram for e6500 and e5500 York Sun
2015-08-17 20:31 ` [U-Boot] [PATCH v1 1/2] powerpc: configs: Fix init_ram physical address for several boards York Sun
2015-09-02 15:22   ` York Sun
2015-08-17 20:31 ` [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram York Sun
2015-09-02 15:22   ` York Sun

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