From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Wed, 2 Sep 2015 10:22:41 -0500 Subject: [U-Boot] [PATCH v1 2/2] powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram In-Reply-To: <1439843512-3285-3-git-send-email-yorksun@freescale.com> References: <1439843512-3285-1-git-send-email-yorksun@freescale.com> <1439843512-3285-3-git-send-email-yorksun@freescale.com> Message-ID: <55E71441.1030407@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 08/17/2015 03:31 PM, York Sun wrote: > MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write > through cache on E6500. L2 cache is enabled to to hold the data. This > patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. > > Signed-off-by: York Sun > Reported-by: Jeffery Zhu > > --- Applied to u-boot-mpc85xx master. Awaiting upstream. York