From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jian Luo <Jian.Luo4@boschrexroth.de>
Date: Wed, 2 Sep 2015 18:27:41 +0200
Subject: [U-Boot] [PATCH] arm: socfpga: dm: Fix DM initialization
 failure after warm reset
In-Reply-To: <201508311528.42937.marex@denx.de>
References: <55E01ECE.6020309@boschrexroth.de>
 <201508282348.04697.marex@denx.de> <55E44FE6.2030901@boschrexroth.de>
 <201508311528.42937.marex@denx.de>
Message-ID: <55E7237D.8050202@boschrexroth.de>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hi!

this error comes again. It isn't a compiler error after all. :(

JTAG inspection shows that the problem is located in 
arch/arm/mach-socfpga/spl.c line94.
It seems that re-enable ECC on OCRAM can cause some strange value 
changes in SRAM.
Disabling ECC might also cause value changes, which I didn't test.

On a cold (re)boot sysmgr_regs->eccgrp_ocram is 0x19 (derr|serr|en). So 
gd keeps intact.

In our VxWorks Image ECC on OCRAM happens to be disabled.
After a warm reset sysmgr_regs->eccgrp_ocram is 0x18 (derr|serr).
Thus after re-enable ECC, gd->dm_root turns to 0x80 every time.

My solution is keeping SYSMGR_ECC_OCRAM_EN bit untouched. And it works 
for me.

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 775a827..c858406 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -90,12 +90,14 @@ void board_init_f(ulong dummy)
          * and DBE might triggered during power on
          */
         reg = readl(&sysmgr_regs->eccgrp_ocram);
-       if (reg & SYSMGR_ECC_OCRAM_SERR)
-               writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
-       if (reg & SYSMGR_ECC_OCRAM_DERR)
-               writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
-                      &sysmgr_regs->eccgrp_ocram);
+       if (reg & SYSMGR_ECC_OCRAM_SERR) {
+               reg &= ~SYSMGR_ECC_OCRAM_SERR;
+               writel(reg, &sysmgr_regs->eccgrp_ocram);
+       }
+       if (reg & SYSMGR_ECC_OCRAM_DERR) {
+               reg &= ~SYSMGR_ECC_OCRAM_DERR;
+               writel(reg, &sysmgr_regs->eccgrp_ocram);
+       }

         memset(__bss_start, 0, __bss_end - __bss_start);

Other solution:
1. Moving OCRAM ECC setting to earlier stage: requires change in generic 
code.
2. Clear gd afterwards: requires replication of every early stage gd 
setting.


Best regards,

Jian Luo
DC-IA/EAH2

Tel.  +49(9352)18-4266

BeQIK
On 31.08.2015 15:28, Marek Vasut wrote:
 > On Monday, August 31, 2015 at 03:00:22 PM, Jian Luo wrote:
 >> Hi,
 >
 > Hi!
 >
 >> On 28.08.2015 23:48, Marek Vasut wrote:
 >>> On Friday, August 28, 2015 at 02:09:15 PM, Jian Luo wrote:
 >>>> Hi Marek,
 >>>
 >>> Hi,
 >>>
 >>>> On 28.08.2015 14:01, Marek Vasut wrote:
 >>>>   > On Friday, August 28, 2015 at 01:40:08 PM, Jian Luo wrote:
 >>>> ----snip----
 >>>>
 >>>>   >> "Security policy". :(
 >>>>   >
 >>>>   > But thunderbird works ? Can't you just copy the SMTP settings from
 >>>>
 >>>> thunderbird
 >>>>
 >>>>   > into gitconfig ? :)
 >>>>
 >>>> I tried w/o success. Might try again another time.
 >>>
 >>> Try using msmtp and configure your git send-email to send through it
 >>> (and all your other MUAs too), it's really convenient :)
 >>
 >> It works. Thanks. :)
 >
 > Cool!
 >
 >>> btw is this a custom board you're porting here ?
 >>
 >> Yes, but this particular error can also be reproduced on Altera SoCDK.
 >>
 >> It seems to be a compiler and/or configuration error of gcc 4.8
 >> generated by yocto dizzy.
 >
 > Let me guess -- gcc 4.8.2 ?
 >
 >> After I switched to gcc 4.9 shiped with Altera Soc EDS 15.0, there is no
 >> warm reset error anymore.
 >
 > Nice, thanks for the update :)
 >
 > Best regards,
 > Marek Vasut