From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC
Date: Wed, 9 Sep 2015 20:37:34 -0700 [thread overview]
Message-ID: <55F0FAFE.1080005@wwwdotorg.org> (raw)
In-Reply-To: <1441705084-5503-1-git-send-email-thierry.reding@gmail.com>
On 09/08/2015 02:38 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Enabling a PLL while IDDQ is high. The Linux kernel checks for this
Is there some word missing in/at-the-end-of that first sentence? It
doesn't seem complete.
> condition and warns about it verbosely, so while this seems to work
> fine, fix it up according to the programming guidelines provided in
> the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
> Sequence").
next prev parent reply other threads:[~2015-09-10 3:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-08 9:38 [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC Thierry Reding
2015-09-08 9:38 ` [U-Boot] [PATCH 2/2] ARM: tegra114: " Thierry Reding
2015-09-08 15:58 ` Tom Warren
2015-09-10 12:09 ` Thierry Reding
2015-09-09 20:40 ` [U-Boot] [PATCH 1/2] ARM: tegra124: " Nicolas Chauvet
2015-09-10 3:37 ` Stephen Warren [this message]
2015-09-10 12:01 ` Thierry Reding
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