From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Wed, 9 Sep 2015 20:37:34 -0700
Subject: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling
	PLLC
In-Reply-To: <1441705084-5503-1-git-send-email-thierry.reding@gmail.com>
References: <1441705084-5503-1-git-send-email-thierry.reding@gmail.com>
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On 09/08/2015 02:38 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Enabling a PLL while IDDQ is high. The Linux kernel checks for this

Is there some word missing in/at-the-end-of that first sentence? It
doesn't seem complete.

> condition and warns about it verbosely, so while this seems to work
> fine, fix it up according to the programming guidelines provided in
> the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
> Sequence").