From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Mon, 14 Sep 2015 07:30:56 +0200 Subject: [U-Boot] [U-Boot, 1/4, v2] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600 In-Reply-To: <20150912152031.GU26226@bill-the-cat> References: <1441196952-13885-1-git-send-email-sr@denx.de> <20150912125043.GT26226@bill-the-cat> <1442068614.2909.58.camel@freescale.com> <20150912144643.GT26226@bill-the-cat> <1442069211.2909.59.camel@freescale.com> <20150912152031.GU26226@bill-the-cat> Message-ID: <55F65B90.8000606@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 12.09.2015 17:20, Tom Rini wrote: > On Sat, Sep 12, 2015 at 09:46:51AM -0500, Scott Wood wrote: >> On Sat, 2015-09-12 at 10:46 -0400, Tom Rini wrote: >>> On Sat, Sep 12, 2015 at 09:36:54AM -0500, Scott Wood wrote: >>>> On Sat, 2015-09-12 at 08:50 -0400, Tom Rini wrote: >>>>> On Wed, Sep 02, 2015 at 02:29:12PM +0200, Stefan Roese wrote: >>>>> >>>>>> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This >>>>>> can >>>>>> be used by boards equipped with a NAND chip that requires 4-bit ECC >>>>>> strength. >>>>>> The SPEAr600 HW ECC only supports 1-bit ECC strength. >>>>>> >>>>>> To enable SW BCH4, you need to specify this in your config header: >>>>>> >>>>>> #define CONFIG_NAND_ECC_BCH >>>>>> #define CONFIG_BCH >>>>>> >>>>>> And use the command "nandecc bch4" to select this ECC scheme upon >>>>>> runtime. >>>>>> >>>>>> Tested on SPEAr600 x600 board. >>>>>> >>>>>> Signed-off-by: Stefan Roese >>>>>> Cc: Scott Wood >>>>>> Acked-by: Viresh Kumar >>>>> >>>>> Applied to u-boot/master, thanks! >>>>> >>>> >>>> There's a v3, and some minor comments even on that one... >>> >>> Mutter, sorry. Would you rather a revert of the series or just >>> incremental on top? >> >> Either is fine -- I just wanted to make sure it didn't get forgotten. > > OK, Stefan, please do an incremental on top of master now to cover > what's been noted in v3, thanks! Sure. Thanks, Stefan