From mboxrd@z Thu Jan 1 00:00:00 1970 From: Przemyslaw Marczak Date: Mon, 21 Sep 2015 15:01:33 +0200 Subject: [U-Boot] [PATCH V2 04/11] Exynos5422/5800: set cpu id to 0x5422 In-Reply-To: <55FFFC4E.6060109@samsung.com> References: <1440770374-11501-1-git-send-email-p.marczak@samsung.com> <1442838403-27777-1-git-send-email-p.marczak@samsung.com> <1442838403-27777-5-git-send-email-p.marczak@samsung.com> <55FFFC4E.6060109@samsung.com> Message-ID: <55FFFFAD.5090603@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Jaehoon, On 09/21/2015 02:47 PM, Jaehoon Chung wrote: > Hi, Przemyslaw. > > On 09/21/2015 09:26 PM, Przemyslaw Marczak wrote: >> The proper CPU ID for those Exynos variants is 0x5422, >> but before the 0x5800 was set. This commit fix this back. >> >> Changes: >> - set cpu id to 0x5422 instead of 0x5800 >> - remove macro proid_is_exynos5800() >> - add macro proid_is_exynos5422() >> - change the calls to proid_is_exynos5800() with new macro >> >> Signed-off-by: Przemyslaw Marczak >> --- >> Changes V2: >> - none >> --- >> arch/arm/mach-exynos/clock.c | 16 ++++++++-------- >> arch/arm/mach-exynos/clock_init_exynos5.c | 2 +- >> arch/arm/mach-exynos/common_setup.h | 4 ++-- >> arch/arm/mach-exynos/include/mach/cpu.h | 6 +++--- >> arch/arm/mach-exynos/include/mach/gpio.h | 4 ++-- >> arch/arm/mach-exynos/pinmux.c | 2 +- >> arch/arm/mach-exynos/power.c | 2 +- >> 7 files changed, 18 insertions(+), 18 deletions(-) >> >> diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c >> index 1c6baa1..2d94851 100644 >> --- a/arch/arm/mach-exynos/clock.c >> +++ b/arch/arm/mach-exynos/clock.c >> @@ -159,8 +159,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) >> div = PLL_DIV_1024; >> else if (proid_is_exynos4412()) >> div = PLL_DIV_65535; >> - else if (proid_is_exynos5250() || proid_is_exynos5420() >> - || proid_is_exynos5800()) >> + else if (proid_is_exynos5250() || proid_is_exynos5420() || >> + proid_is_exynos5422()) >> div = PLL_DIV_65536; >> else >> return 0; >> @@ -346,7 +346,7 @@ static struct clk_bit_info *get_clk_bit_info(int peripheral) >> int i; >> struct clk_bit_info *info; >> >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> info = exynos542x_bit_info; >> else >> info = exynos5_bit_info; >> @@ -558,7 +558,7 @@ static unsigned long exynos542x_get_periph_rate(int peripheral) >> unsigned long clock_get_periph_rate(int peripheral) >> { >> if (cpu_is_exynos5()) { >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> return exynos542x_get_periph_rate(peripheral); >> return exynos5_get_periph_rate(peripheral); >> } else { >> @@ -1576,7 +1576,7 @@ static unsigned long exynos4_get_i2c_clk(void) >> unsigned long get_pll_clk(int pllreg) >> { >> if (cpu_is_exynos5()) { >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> return exynos542x_get_pll_clk(pllreg); >> return exynos5_get_pll_clk(pllreg); >> } else if (cpu_is_exynos4()) { >> @@ -1694,7 +1694,7 @@ void set_mmc_clk(int dev_index, unsigned int div) >> div -= 1; >> >> if (cpu_is_exynos5()) { >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> exynos5420_set_mmc_clk(dev_index, div); >> else >> exynos5_set_mmc_clk(dev_index, div); >> @@ -1710,7 +1710,7 @@ unsigned long get_lcd_clk(void) >> } else if (cpu_is_exynos5()) { >> if (proid_is_exynos5420()) >> return exynos5420_get_lcd_clk(); >> - else if (proid_is_exynos5800()) >> + else if (proid_is_exynos5422()) >> return exynos5800_get_lcd_clk(); >> else >> return exynos5_get_lcd_clk(); >> @@ -1742,7 +1742,7 @@ void set_mipi_clk(void) >> int set_spi_clk(int periph_id, unsigned int rate) >> { >> if (cpu_is_exynos5()) { >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> return exynos5420_set_spi_clk(periph_id, rate); >> return exynos5_set_spi_clk(periph_id, rate); >> } >> diff --git a/arch/arm/mach-exynos/clock_init_exynos5.c b/arch/arm/mach-exynos/clock_init_exynos5.c >> index 0200fd1..1b7498d 100644 >> --- a/arch/arm/mach-exynos/clock_init_exynos5.c >> +++ b/arch/arm/mach-exynos/clock_init_exynos5.c >> @@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void) >> >> void system_clock_init(void) >> { >> - if (proid_is_exynos5420() || proid_is_exynos5800()) >> + if (proid_is_exynos5420() || proid_is_exynos5422()) >> exynos5420_system_clock_init(); >> else >> exynos5250_system_clock_init(); >> diff --git a/arch/arm/mach-exynos/common_setup.h b/arch/arm/mach-exynos/common_setup.h >> index 67aac2d..2829fb2 100644 >> --- a/arch/arm/mach-exynos/common_setup.h >> +++ b/arch/arm/mach-exynos/common_setup.h >> @@ -78,7 +78,7 @@ static inline void configure_l2_ctlr(void) >> CACHE_TAG_RAM_LATENCY_2_CYCLES | >> CACHE_DATA_RAM_LATENCY_2_CYCLES; >> >> - if (proid_is_exynos5420() || proid_is_exynos5800()) { >> + if (proid_is_exynos5420() || proid_is_exynos5422()) { >> val |= CACHE_ECC_AND_PARITY | >> CACHE_TAG_RAM_LATENCY_3_CYCLES | >> CACHE_DATA_RAM_LATENCY_3_CYCLES; >> @@ -97,7 +97,7 @@ static inline void configure_l2_actlr(void) >> { >> uint32_t val; >> >> - if (proid_is_exynos5420() || proid_is_exynos5800()) { >> + if (proid_is_exynos5420() || proid_is_exynos5422()) { >> mrc_l2_aux_ctlr(val); >> val |= CACHE_ENABLE_FORCE_L2_LOGIC | >> CACHE_DISABLE_CLEAN_EVICT; >> diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h >> index cb3d2cc..14a1692 100644 >> --- a/arch/arm/mach-exynos/include/mach/cpu.h >> +++ b/arch/arm/mach-exynos/include/mach/cpu.h >> @@ -237,7 +237,7 @@ static inline void s5p_set_cpu_id(void) >> * Exynos5800 is a variant of Exynos5420 >> * and has product id 0x5422 >> */ > > Needs to modify the above comment? > > Best Regards, > Jaehoon Chung > Thanks! Will fix in next version. Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marczak at samsung.com