From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan Roese Date: Tue, 29 Sep 2015 09:02:50 +0200 Subject: [U-Boot] [PATCH 2/2] spi: Add SPI NOR protection mechanism In-Reply-To: <1443494753-3647-2-git-send-email-festevam@gmail.com> References: <1443494753-3647-1-git-send-email-festevam@gmail.com> <1443494753-3647-2-git-send-email-festevam@gmail.com> Message-ID: <560A379A.7080102@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Fabio, On 29.09.2015 04:45, Fabio Estevam wrote: > From: Fabio Estevam > > Many SPI flashes have protection bits (BP2, BP1 and BP0) in the > status register that can protect selected regions of the SPI NOR. > > Take these bits into account when performing erase operations, > making sure that the protected areas are skipped. > > Introduce the CONFIG_SF_STM_PROTECT option that can be selected > by systems that want to protect regions of SPI NOR flash using > the same programming model as in the ST Micro SPI NOR flashes, like > for example the M25P32. > > Based on the implementation from Brian Norris > for the Linux kernel: > https://patchwork.ozlabs.org/patch/513041/ > > Tested on a mx6qsabresd: > > => sf probe > SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB > => sf protect on 0x3f0000 0x10000 > => sf erase 0x3f0000 0x10000 > offset 0x3f0000 is protected and cannot be erased > SF: 65536 bytes @ 0x3f0000 Erased: ERROR > => sf protect off 0x3f0000 0x10000 > => sf erase 0x3f0000 0x10000 > SF: 65536 bytes @ 0x3f0000 Erased: OK > > Signed-off-by: Fabio Estevam > --- > > README | 12 +++ > common/cmd_sf.c | 30 +++++++ > drivers/mtd/spi/sf_internal.h | 6 -- > drivers/mtd/spi/sf_ops.c | 188 ++++++++++++++++++++++++++++++++++++++++++ > include/spi_flash.h | 25 +++++- > 5 files changed, 253 insertions(+), 8 deletions(-) > > diff --git a/README b/README > index a13705a..3411ea9 100644 > --- a/README > +++ b/README > @@ -3068,6 +3068,18 @@ CBFS (Coreboot Filesystem) support > memories can be connected with a given cs line. > Currently Xilinx Zynq qspi supports these type of connections. > > + CONFIG_SF_STM_PROTECT > + > + Enable the built-in protection mechanism provided by the > + BP2, BP1 and BP0 bits from the status register present > + on ST-Micro flashes such as M25P32. Please refer to the > + M25P32 datasheet to understand how to program these bits > + in order to protect a selected region of the SPI NOR flash. > + This same bit protection programming model applies to SPI > + NOR flashes from other manufacturers such as: > + - Micron M25P32 > + - SST SST25V32B We should not add more CONFIG_ descriptions to this README. Please add this option via Kconfig (in drivers/mtd/spi/Kconfig) and add its description there as well. Thanks, Stefan